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| LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 Features Non-volatile, Infinitely Reconfigurable * Instant-on - powers up in microseconds * No external configuration memory * Excellent design security, no bit stream to intercept * Reconfigure SRAM based logic in milliseconds * SRAM and non-volatile memory programmable through system configuration and JTAG ports Flexible I/O Buffer * Programmable sysIOTM buffer supports wide range of interfaces: - LVCMOS 3.3/2.5/1.8/1.5/1.2 - LVTTL - SSTL 18 Class I - SSTL 3/2 Class I, II - HSTL15 Class I, III - HSTL 18 Class I, II, III - PCI - LVDS, Bus-LVDS, LVPECL, RSDS Sleep Mode * Allows up to 1000x static current reduction TransFRTM Reconfiguration (TFR) * In-field logic update while system operates Dedicated DDR Memory Support * Implements interface up to DDR333 (166MHz) Extensive Density and Package Options * 3.1K to 19.7K LUT4s * 62 to 340 I/Os * Density migration supported sysCLOCKTM PLLs * Up to 4 analog PLLs per device * Clock multiply, divide and phase shifting System Level Support * IEEE Standard 1149.1 Boundary Scan, plus ispTRACYTM internal logic analyzer capability * Onboard oscillator for configuration * Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply Embedded and Distributed Memory * 54 Kbits to 396 Kbits sysMEMTM Embedded Block RAM * Up to 79 Kbits distributed RAM * Flexible memory resources: - Distributed and block memory Table 1-1. LatticeXP Family Selection Guide Device PFU/PFF Rows PFU/PFF Columns PFU/PFF (Total) LUTs (K) Distributed RAM (KBits) EBR SRAM (KBits) EBR SRAM Blocks VCC Voltage PLLs Max. I/O Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 144-pin TQFP (20 x 20 mm) 208-pin PQFP (28 x 28 mm) 256-ball fpBGA (17 x 17 mm) 388-ball fpBGA (23 x 23 mm) 484-ball fpBGA (23 x 23 mm) 62 100 136 100 142 188 LFXP3 16 24 384 3 12 54 6 1.2/1.8/2.5/3.3V 2 136 LFXP6 24 30 720 6 23 72 8 1.2/1.8/2.5/3.3V 2 188 LFXP10 32 38 1216 10 39 216 24 1.2/1.8/2.5/3.3V 4 244 LFXP15 40 48 1932 15 61 324 36 1.2/1.8/2.5/3.3V 4 300 LFXP20 44 56 2464 20 79 396 44 1.2/1.8/2.5/3.3V 4 340 188 244 188 268 300 188 268 340 (c) 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1001 Introduction_01.5a July 6, 2007 3:01 p.m. Lattice Semiconductor Introduction LatticeXP Family Data Sheet Introduction The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs. The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXPTM technology. With this technology, expensive external configuration memories are not required and designs are secured from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications. The ispLEVER(R) design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORETM modules for the LatticeXP family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeXP Family Data Sheet Architecture July 2007 Data Sheet DS1001 Architecture Overview The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 21. On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIGTM peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memories are not required and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an "instant-on" capability that allows easy interfacing in many applications. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the outside rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every three rows of PFF blocks there is a row of PFU blocks. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM or ROM. The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeXP architecture provides up to four PLLs per device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from 3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system. (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1001 Architecture_02.0 July 6, 2007 3:03 p.m. Lattice Semiconductor Figure 2-1. LatticeXP Top Level Block Diagram Programmable I/O Cell (PIC) includes sysIO Interface Architecture LatticeXP Family Data Sheet sysMEM Embedded Block RAM (EBR) Non-volatile Memory JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (PFU without RAM) sysCLOCK PLL Programmable Functional Unit (PFU) PFU and PFF Blocks The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-2. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 Slice 1 Slice 2 Slice 3 D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch To Routing 2-2 Lattice Semiconductor Slice Architecture LatticeXP Family Data Sheet Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. Figure 2-3. Slice Diagram To / From Different slice / PFU Fast Carry In (FCI) Slice OFX1 A1 B1 C1 D1 CO F1 F SUM D LUT4 & CARRY CI FF/ Latch Q1 To Routing From Routing M1 M0 LUT Expansion Mux OFX0 A0 B0 CO C0 D0 LUT4 & CARRY CI F SUM OFX0 D F0 FF/ Latch Q0 Control Signals selected and inverted per slice in routing CE CLK LSR Note: Some interslice signals are not shown. To / From Different slice / PFU Fast Carry Out (FCO) 2-3 Lattice Semiconductor Table 2-1. Slice Signal Descriptions Function Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 Inputs to LUT4 A1, B1, C1, D1 Inputs to LUT4 M0 M1 CE LSR CLK FCIN F0, F1 Q0, Q1 OFX0 OFX1 FCO Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry In1 Architecture LatticeXP Family Data Sheet Description LUT4 output register bypass signals Register Outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice For the right most PFU the fast carry chain output1 1. See Figure 2-2 for connection details. 2. Requires two PFUs. Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic PFU Slice PFF Slice LUT 4x2 or LUT 5x1 LUT 4x2 or LUT 5x1 Ripple 2-bit Arithmetic Unit 2-bit Arithmetic Unit RAM SP 16x2 N/A ROM ROM 16x1 x 2 ROM 16x1 x 2 Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: * * * * * * * Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. 2-4 Lattice Semiconductor Architecture LatticeXP Family Data Sheet The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required for Implementing Distributed RAM SPR16x2 Number of Slices 1 DPR16x2 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM Figure 2-4. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK DPR16x2 DO0 DO1 WAD0 WAD1 WAD2 WAD3 DI0 DI1 WCK WRE RAD0 RAD1 RAD2 RAD3 RDO0 RDO1 WDO0 WDO1 ROM16x1 AD0 AD1 AD2 AD3 DO0 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. 2-5 Lattice Semiconductor Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT 6x 2 or MUX 8x1 x 2 LUT 7x1 or MUX 16x1 x 1 Ripple 2-bit Add x 4 2-bit Sub x 4 2-bit Counter x 4 2-bit Comp x 4 RAM1 SPR16x2 x 4 DPR16x2 x 2 SPR16x4 x 2 DPR16x4 x 1 SPR16x8 x 1 Architecture LatticeXP Family Data Sheet ROM ROM16x1 x 8 ROM16x2 x 4 ROM16x4 x 2 ROM16x8 x 1 1. These modes are not available in PFF blocks Routing There are many resources provided in the LatticeXP devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The x2 and x6 resources are buffered allowing both short and long connections routing between PFUs. The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock Distribution Network The clock inputs are selected from external I/O, the sysCLOCKTM PLLs or routing. These clock inputs are fed through the chip via a clock distribution system. Primary Clock Sources LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. LatticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources. 2-6 Lattice Semiconductor Figure 2-5. Primary Clock Sources From Routing Clock Input From Routing Architecture LatticeXP Family Data Sheet PLL Input PLL PLL PLL Input Clock Input 20 Primary Clock Sources To Quadrant Clock Selection Clock Input PLL Input PLL PLL PLL Input From Routing Clock Input From Routing Note: Smaller devices have two PLLs. Secondary Clock Sources LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6. 2-7 Lattice Semiconductor Figure 2-6. Secondary Clock Sources From Routing From Routing Clock Input From Routing Architecture LatticeXP Family Data Sheet From Routing From Routing From Routing From Routing From Routing Clock Input 20 Secondary Clock Sources To Quadrant Clock Selection Clock Input From Routing From Routing From Routing From Routing From Routing From Routing Clock Input From Routing From Routing Clock Routing The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 28. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 29. Figure 2-7. Per Quadrant Primary Clock Selection 20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1 DCS2 DCS2 4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant 1. Smaller devices have fewer PLL related lines. 2. Dynamic clock select. 2-8 Lattice Semiconductor Figure 2-8. Per Quadrant Secondary Clock Selection Architecture LatticeXP Family Data Sheet 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals 4 Secondary Clocks per Quadrant Figure 2-9. Slice Clock Selection Primary Clock Secondary Clock Routing GND Clock to Each Slice sysCLOCK Phase Locked Loops (PLLs) The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback signals to the feedback divider: from CLKOP (PLL internal), from clock net (CLKOP or CLKOS) or from a user clock (PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-10 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. 2-9 Lattice Semiconductor Figure 2-10. PLL Diagram Dynamic Delay Adjustment Architecture LatticeXP Family Data Sheet LOCK RST CLKI (from routing or external pin) Input Clock Divider (CLKI) Delay Adjust Voltage Controlled VCO Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOS CLKOP Feedback Divider (CLKFB) Secondary Clock Divider (CLKOK) CLKFB from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) CLKOK Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block. Figure 2-11. PLL Primitive RST CLKI CLKFB CLKOP CLKOS CLKOK EPLLB CLKOP LOCK CLKI CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] EHXPLLB LOCK DDAOZR DDAOLAG DDAODEL[2:0] Table 2-5. PLL Signal Descriptions Signal CLKI CLKFB RST CLKOS CLKOP CLKOK LOCK DDAMODE DDAIZR DDAILAG DDAIDEL[2:0] DDAOZR DDAOLAG DDAODEL[2:0] I/O I I I O O O O I I I I O O O Clock input from external pin or routing PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) "1" to reset input clock divider PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (No phase shift) PLL output to clock tree through secondary clock divider "1" indicates PLL LOCK to CLKI Dynamic Delay Enable. "1" Pin control (dynamic), "0": Fuse Control (static) Dynamic Delay Zero. "1": delay = 0, "0": delay = on Dynamic Delay Lag/Lead. "1": Lag, "0": Lead Dynamic Delay Input Dynamic Delay Zero Output Dynamic Delay Lag/Lead Output Dynamic Delay Output Description 2-10 Lattice Semiconductor Architecture LatticeXP Family Data Sheet For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates the DCS Block Macro. Figure 2-12. DCS Block Primitive CLK0 CLK1 SEL DCS DCSOUT Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information on the DCS, please see details of additional technical documentation at the end of this data sheet. Figure 2-13. DCS Waveforms CLK0 CLK1 SEL DCSOUT sysMEM Memory The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. 2-11 Lattice Semiconductor Table 2-6. sysMEM Block Configurations Memory Mode Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 Architecture LatticeXP Family Data Sheet Single Port True Dual Port Pseudo Dual Port Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-14 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. 2-12 Lattice Semiconductor Figure 2-14. sysMEM Memory Primitives ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0] Architecture LatticeXP Family Data Sheet AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] EBR EBR ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0] Single Port RAM True Dual Port RAM AD[12:0] CLK CE RST CS[2:0] EBR ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0] ADR[12:0] EBR DO[35:0] CER CLKR ROM Pseudo-Dual Port RAM The EBR memory supports three forms of write behavior for single port or dual port operation: 1. Normal - data on the output appears only during read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through - a copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. 3. Read-Before-Write - when new data is being written, the old content of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-15. 2-13 Lattice Semiconductor Figure 2-15. Memory Core Reset Memory Core SET Architecture LatticeXP Family Data Sheet D Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information on sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the EBR is always asynchronous. Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. Programmable I/O Cells (PICs) Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO buffer, and receives input from the buffer. 2-14 Lattice Semiconductor Figure 2-17. PIC Diagram Architecture LatticeXP Family Data Sheet PIO A TD OPOS1 ONEG1 TD D0 D1 DDRCLK IOLT0 Tristate DO Register Block (2 Flip Flops) OPOS0 ONEG0 D0 D1 DDRCLK PADA "T" IOLD0 Output Register Block (2 Flip Flops) sysIO Buffer INCK INDD INFF IPOS0 IPOS1 Control Muxes INCK INDD INFF IPOS0 IPOS1 DI CLK CE LSR GSRN DQS DDRCLKPOL CLKO CEO LSR GSR CLKI CEI Input Register Block (5 Flip Flops) PADB "C" PIO B In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs, one PIC pair and one single I/O, as shown in Figure 2-18. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as "T" and "C"). The PAD Labels "T" and "C" distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. One of every 14 PIOs (a group of 8 PICs) contains a delay element to facilitate the generation of DQS signals as shown in Figure 2-19. The DQS signal feeds the DQS bus which spans the set of 13 PIOs (8 PICs). The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight bits of data. The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Additional detail is provided in the Signal Descriptions table in this data sheet. 2-15 Lattice Semiconductor Figure 2-18. Group of Seven PIOs PIO A PIO B PIO A PIO B Four PICs PIO A PIO B PIO A Architecture LatticeXP Family Data Sheet PADA "T" LVDS Pair PADB "C" PADA "T" PADB "C" PADA "T" LVDS Pair One PIO Pair PADB "C" PADA "T" Figure 2-19. DQS Routing PIO A PIO B PIO A PIO B PIO A PIO B PIO A PADA "T" LVDS Pair PADB "C" PADA "T" PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" PIO B PIO A PIO B PIO A PIO B PIO A PIO B sysIO Buffer Delay PADB "C" Assigned DQS Pin DQS PADA "T" LVDS Pair PADB "C" PADA "T" PADB "C" PADA "T" LVDS Pair PADB "C" PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data signals are also included in these blocks. Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-20 shows the diagram of the input register block. Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and 2-16 Lattice Semiconductor Architecture LatticeXP Family Data Sheet in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time requirement when using a global clock. The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primitives. The SDR/SYNC registers have reset and clock enable available. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic, see the DDR memory section of this data sheet. Figure 2-20. Input Register Diagram DI (From sysIO Buffer) INCK INDD Delay Block Fixed Delay DDR Registers SDR & Sync Registers D0 D Q D-Type Q D D-Type /LATCH D2 D Q D Q D-Type /LATCH To Routing IPOS0 D Q D1 IPOS1 D-Type DQS Delayed (From DQS Bus) D-Type CLK0 (From Routing) DDRCLKPOL (From DDR Polarity Control Bus) 2-17 Lattice Semiconductor Figure 2-21. Input Register DDR Waveforms DI (In DDR Mode) DQS DQS Delayed A B C D Architecture LatticeXP Family Data Sheet E F D0 B D D2 A C Figure 2-22. INDDRXB Primitive D ECLK LSR SCLK CE DDRCLKPOL IDDRXB QB QA Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-23 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a Dtype or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available. 2-18 Lattice Semiconductor Figure 2-23. Output Register Block Architecture LatticeXP Family Data Sheet ONEG0 Q D D-Type /LATCH 0 OUTDDN 0 1 DO From Routing 1 OPOS0 D Q To sysIO Buffer LATCH LE* CLK1 Programmed Control *Latch is transparent when input is low. Figure 2-24. ODDRXB Primitive DA DB CLK LSR ODDRXB Q Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). 2-19 Lattice Semiconductor Figure 2-25. Tristate Register Block Architecture LatticeXP Family Data Sheet TD OUTDDN ONEG1 Q D D-Type /LATCH 0 0 1 1 TO From Routing OPOS1 D Q To sysIO Buffer LATCH LE* CLK1 Programmed Control *Latch is transparent when input is low. Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from the programmable DQS pin. The clock can optionally be inverted. The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate signal is passed through this block. DDR Memory Support Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input (for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeXP devices provide this capability. In addition to these registers, the LatticeXP devices contain two elements to simplify the design of input structures for read operations: the DQS delay block and polarity control logic. DLL Calibrated DQS Delay Block Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock (referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds the polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. Figures 2-26 and 2-27 show how the polarity control logic are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration (6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of the device as shown in Figure 2-27. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. 2-20 Lattice Semiconductor Figure 2-26. DQS Local Bus Architecture LatticeXP Family Data Sheet Delay Control Bus Polarity Control Bus DQS Bus DQS GSR CLKI CEI DQS PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. sysIO Buffer DDR Datain PAD DI To DDR Reg. PIO sysIO Buffer DQS Strobe PAD DI Polarity Control Logic DQS DQSDEL Calibration Bus from DLL Figure 2-27. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus Polarity Control Signal Bus DQS Signal Bus DLL DLL 2-21 Lattice Semiconductor Polarity Control Logic Architecture LatticeXP Family Data Sheet In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeXP family contains dedicated circuits to transfer data between these domains. To prevent setup and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of the each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to control the polarity of the clock to the synchronizing registers. sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today's systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysIO Buffer Banks LatticeXP devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each bank to be completely independent from each other. Figure 2-28 shows the eight banks and their associated supplies. In the LatticeXP devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-X) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as a fixed threshold input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeXP devices have a VCC core logic power supply, and a VCCAUX supply that power all differential and referenced buffers. Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank's supply and reference voltages. 2-22 Lattice Semiconductor Figure 2-28. LatticeXP Banks GND VREF2(0) GND VREF2(1) VCCIO0 1 1 Architecture LatticeXP Family Data Sheet VCCIO7 VREF1(7) VREF2(7) GND VCCIO6 V REF1(6) V REF2(6) GND Bank 0 VREF1(0) VREF1(1) VCCIO1 1 N Bank 1 N 1 VCCIO2 VREF1(2) VREF2(2) GND VCCIO3 VREF1(3) VREF2(3) GND Bank 7 Bank 2 M 1 M 1 Bank 3 Bank 6 M 1 M Bank 5 N 1 Bank 4 N VREF1(4) VREF2(4) VREF2(5) V REF1(5) VCCIO5 VCCIO4 GND Note: N and M are the maximum number of I/Os per bank. LatticeXP devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only) The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. Only the I/Os on the top and bottom banks have PCI clamps. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid operating levels and the device has been configured. 2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs) The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The referenced input buffer can also be configured as a differential input. In these banks the two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Select I/Os in the left and right banks have LVDS differential output drivers. Refer to the Logic Signal Connections tables for more information. 2-23 GND Lattice Semiconductor Architecture LatticeXP Family Data Sheet Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user's responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-up to VCCIO. The I/O pins will not take on the user configuration until VCC, VCCAUX and VCCIO have reached satisfactory levels at which time the I/Os will take on the user-configured settings. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered up before or together with the VCC and VCCAUX supplies. Supported Standards The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS, LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. Table 2-7. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS332 LVCMOS252 LVCMOS18 LVCMOS15 LVCMOS12 PCI HSTL18 Class I, II HSTL18 Class III HSTL15 Class I HSTL15 Class III SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I Differential Interfaces Differential SSTL18 Class I Differential SSTL2 Class I, II Differential SSTL3 Class I, II Differential HSTL15 Class I, III Differential HSTL18 Class I, II, III LVDS, LVPECL BLVDS -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 VREF (Nom.) -- -- -- -- -- -- -- 0.9 1.08 0.75 0.9 1.5 1.25 0.9 VCCIO1 (Nom.) -- -- -- 1.8 1.5 -- 3.3 -- -- -- -- -- -- -- 1. When not specified VCCIO can be set anywhere in the valid operating range. 2. JTAG inputs do not have a fixed threshold option and always follow VCCJ. 2-24 Lattice Semiconductor Table 2-8. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II, III HSTL15 Class I, III SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I Differential Interfaces Differential SSTL3, Class I, II Differential SSTL2, Class I, II Differential SSTL18, Class I Differential HSTL18, Class I, II, III Differential HSTL15, Class I, III LVDS BLVDS1 LVPECL1 1. Emulated with external resistors. Architecture LatticeXP Family Data Sheet Drive 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 8mA 2mA. 6mA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCIO (Nom.) 3.3 3.3 2.5 1.8 1.5 1.2 -- -- -- -- -- 3.3 1.8 1.5 3.3 2.5 1.8 3.3 2.5 1.8 1.8 1.5 2.5 2.5 3.3 Hot Socketing The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits, which allows easy integration with the rest of the system. These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications. Sleep Mode The LatticeXP "C" devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the SLEEPN pin. During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os are tri-stated. Do not enter Sleep Mode during device programming or configuration operation. In Sleep Mode, power supplies can be maintained in their normal operating range, eliminating the need for external switching of power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes. 2-25 Lattice Semiconductor Table 2-9. Characteristics of Normal, Off and Sleep Modes Characteristic SLEEPN Pin Static Icc I/O Leakage Power Supplies VCC/VCCIO/VCCAUX Logic Operation I/O Operation JTAG and Programming circuitry EBR Contents and Registers Normal High Typical <100mA <10A Normal Range User Defined User Defined Operational Maintained Off -- 0 <1mA Off Architecture LatticeXP Family Data Sheet Sleep Low Typical <100uA <10A Normal Range Non operational Tri-state Non-operational Non-maintained Non Operational Tri-state Non-operational Non-maintained SLEEPN Pin Characteristics The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the device. This pin also has a weak pull-up typically in the order of 10A along with a Schmidt trigger and glitch filter to prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC specifications portion of this data sheet show a detailed timing diagram. Configuration and Testing The following section describes the configuration and testing features of the LatticeXP family of devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. Device Configuration All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The non-volatile memory in the LatticeXP can be configured in three different modes: * In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode. * In 1532 mode via the 1149.1 port. * In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes place. The SRAM configuration memory can be configured in three different ways: * At power-up via the on-chip non-volatile memory. * In 1532 mode via the 1149.1 port SRAM direct configuration. * In sysCONFIG mode via the sysCONFIG port SRAM direct configuration. 2-26 Lattice Semiconductor Architecture LatticeXP Family Data Sheet Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the LatticeXP devices. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the TAP port. Leave Alone I/O When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility for implementing systems where reprogramming occurs onthe-fly. TransFR (Transparent Field Reconfiguration) TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Interruption During Configuration Using TransFR Technology, for details. Security The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM configuration and non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space. For more information on device configuration, please see details of additional technical documentation at the end of this data sheet. Figure 2-29. ispXP Block Diagram ISP 1149.1 TAP Port Port sysCONFIG Peripherial Port BACKGND 1532 sysCONFIG Mode Program in seconds Configure in milliseconds Power-up Memory Space Refresh SRAM Memory Space Download in microseconds Memory Space Internal Logic Analyzer Capability (ispTRACY) All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice's ispTRACY. The ispTRACY utility is added into the user design at compile time. For more information on ispTRACY, please see information regarding additional technical documentation at the end of this data sheet. Oscillator Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configuration. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the 2-27 Lattice Semiconductor Architecture LatticeXP Family Data Sheet master serial clock is 2.5MHz. Table 2-10 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is selected during the design process, the following sequence takes place: 1. User selects a different Master Serial Clock frequency for configuration. 2. During configuration the device starts with the default (2.5MHz) Master Serial Clock frequency. 3. The clock configuration settings are contained in the early configuration bit stream. 4. The Master Serial Clock frequency changes to the selected frequency once the clock configuration bits are received. For further information on the use of this oscillator for configuration, please see details of additional technical documentation at the end of this data sheet. Table 2-10. Selectable Master Serial Clock (CCLK) Frequencies During Configuration CCLK (MHz) 2.5 1 CCLK (MHz) 13 15 20 26 30 34 41 CCLK (MHz) 45 51 55 60 130 -- -- 4.3 5.4 6.9 8.1 9.2 10.0 1. Default Density Shifting The LatticeXP family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-28 LatticeXP Family Data Sheet DC and Switching Characteristics November 2007 Data Sheet DS1001 Absolute Maximum Ratings1, 2, 3, 4 XPE (1.2V) XPC (1.8V/2.5V/3.3V) Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCP . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V I/O Tristate Voltage Applied5 . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V Dedicated Input Voltage Applied 5 . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150C . . . . . . . . . . . . . . . -65 to 150C Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125C . . . . . . . . . . . . . . . . . . . +125C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions outside of those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. All chip grounds are connected together to a common package GND plane. 5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns. Recommended Operating Conditions3 Symbol VCC VCCP VCCAUX4 VCCIO1, 2 VCCJ1 tJCOM tJIND tJFLASHCOM tJFLASHIND Parameter Core Supply Voltage for 1.2V Devices Core Supply Voltage for 1.8V/2.5V/3.3V Devices Supply Voltage for PLL for 1.2V Devices Supply Voltage for PLL for 1.8V/2.5V/3.3V Devices Auxiliary Supply Voltage I/O Driver Supply Voltage Supply Voltage for IEEE 1149.1 Test Access Port Junction Temperature, Commercial Operation Junction Temperature, Industrial Operation Junction Temperature, Flash Programming, Commercial Junction Temperature, Flash Programming, Industrial Min. 1.14 1.71 1.14 1.71 3.135 1.14 1.14 0 -40 0 0 Max. 1.26 3.465 1.26 3.465 3.465 3.465 3.465 85 100 85 85 Units V V V V V V V C C C C 1. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. For the XPE devices (1.2V VCC), if VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. 2. See recommended voltages by I/O standard in subsequent table. 3. The system designer must ensure that the FPGA design stays within the specified junction temperature and package thermal capabilities of the device based on the expected operating frequency, activity factor and environment conditions of the system. 4. VCCAUX ramp rate must not exceed 30mV/s during power up when transitioning between 0V and 3.3V. (c) 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1001 DC and Switching_02.7 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Hot Socketing Specifications1, 2, 3, 4, 5, 6 Symbol IDK 1. 2. 3. 4. 5. 6. Parameter Input or I/O Leakage Current Condition 0 VIN VIH (MAX.) Min. -- Typ. -- Max. +/-1000 Units A Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO. 0 VCC VCC (MAX) or 0 VCCAUX VCCAUX (MAX). 0 VCCIO VCCIO (MAX) for top and bottom I/O banks. 0.2 VCCIO VCCIO (MAX) for left and right I/O banks. IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. 3-2 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Condition 0 VIN (VCCIO - 0.2V) (VCCIO - 0.2V) < VIN 3.6V 0 VIN 0.7 VCCIO VIL (MAX) VIN VIH (MAX) VIN = VIL (MAX) 0 VIN VIH (MAX) 0 VIN VIH (MAX) 0 VIN VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) Min. -- -- -30 30 30 -30 -- -- VIL (MAX) -- -- Typ. -- -- -- -- -- -- -- -- -- 8 8 Max. 10 40 -150 150 -- -- 150 -150 VIH (MIN) -- -- Units A A A A A A A A V pf pf IIL, IIH1, 2, 4 Input or I/O Leakage IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 I/O Active Pull-up Current I/O Active Pull-down Current Bus Hold Low sustaining current Bus Hold Low Overdrive current Bus Hold High Overdrive current Bus Hold trip Points I/O Capacitance 3 Bus Hold High sustaining current VIN = 0.7VCCIO Dedicated Input Capacitance3 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. Not applicable to SLEEPN/TOE pin. 3. TA 25C, f = 1.0MHz 4. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can be expected on the high-to-low transition. Supply Current (Sleep Mode)1, 2, 3 Symbol Parameter Device LFXP3C LFXP6C ICC Core Power Supply LFXP10C LFXP15C LFXP20C ICCP PLL Power Supply (per PLL) All LFXP `C' Devices LFXP3C LFXP6C ICCAUX Auxiliary Power Supply LFXP10C LFXP15C LFXP20C LFXP3C LFXP6C ICCIO Bank Power Supply 5 Typ.4 12 14 16 18 20 1 2 2 2 3 4 2 2 2 3 4 1 Max 65 75 85 95 105 5 90 100 110 120 130 20 22 24 27 30 5 Units A A A A A A A A A A A A A A A A A LFXP10C LFXP15C LFXP20C ICCJ 1. 2. 3. 4. 5. VCCJ Power Supply All LFXP `C' Devices Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. User pattern: blank. TA=25C, power supplies at nominal voltage. Per bank. 3-3 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter Device LFXP3E LFXP6E LFXP10E LFXP15E ICC Core Power Supply LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C ICCP PLL Power Supply (per PLL) All LFXP3E/C LFXP6E/C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V LFXP10E/C LFXP15E/C LFXP20E/C ICCIO ICCJ 1. 2. 3. 4. 5. 6. Typ.5 15 20 35 45 55 35 40 70 80 90 8 22 22 30 30 30 2 1 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Bank Power Supply6 VCCJ Power Supply All All For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. User pattern: blank. TA=25C, power supplies at nominal voltage. Per bank. 3-4 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Initialization Supply Current1, 2, 3, 4, 5, 6 Over Recommended Operating Conditions Symbol Parameter Device LFXP3E LFXP6E LFXP10E LFXP15E ICC Core Power Supply LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V LFXP10E /C LFXP15E /C LFXP20E /C ICCJ 1. 2. 3. 4. 5. 6. 7. Typ.7 40 50 110 140 250 60 70 150 180 290 50 60 90 110 130 2 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VCCJ Power Supply All Until DONE signal is active. For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Typical user pattern. Assume normal bypass capacitor/decoupling capacitor across the supply. TA=25C, power supplies at nominal voltage. 3-5 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Programming and Erase Flash Supply Current1, 2, 3, 4, 5 Symbol Parameter Device LFXP3E LFXP6E LFXP10E LFXP15E ICC Core Power Supply LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V LFXP10E /C LFXP15E /C LFXP20E /C ICCJ 1. 2. 3. 4. 5. 6. 7. Typ.6 30 40 50 60 70 50 60 90 100 110 50 60 90 110 130 2 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VCCJ Power Supply7 All For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Blank user pattern; typical Flash pattern. Bypass or decoupling capacitor across the supply. JTAG programming is at 1MHz. TA=25C, power supplies at nominal voltage. When programming via JTAG. 3-6 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet sysIO Recommended Operating Conditions VCCIO Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL PCI33 SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL15 Class III HSTL 18 Class I, II HSTL 18 Class III LVDS LVPECL1 BLVDS1 Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 1.71 2.375 3.135 1.425 1.425 1.71 1.71 2.375 3.135 2.375 Typ. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 1.8 2.5 3.3 1.5 1.5 1.8 1.8 2.5 3.3 2.5 Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 1.89 2.625 3.465 1.575 1.575 1.89 1.89 2.625 3.465 2.625 Min. -- -- -- -- -- -- -- 0.833 1.15 1.3 0.68 -- -- -- -- -- -- VREF (V) Typ. -- -- -- -- -- -- -- 0.9 1.25 1.5 0.75 0.9 0.9 1.08 -- -- -- Max. -- -- -- -- -- -- -- 0.969 1.35 1.7 0.9 -- -- -- -- -- -- 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 3-7 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet sysIO Single-Ended DC Electrical Characteristics Input/Output Standard LVCMOS 3.3 VIL Min. (V) -0.3 Max. (V) 0.8 VIH Min. (V) 2.0 Max. (V) 3.6 VOL Max. (V) 0.4 0.2 LVTTL -0.3 0.8 2.0 3.6 0.4 0.2 LVCMOS 2.5 -0.3 0.7 1.7 3.6 0.4 0.2 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 ("C" Version) LVCMOS 1.2 ("E" Version) PCI SSTL3 class I SSTL3 class II SSTL2 class I SSTL2 class II SSTL18 class I HSTL15 class I HSTL15 class III HSTL18 class I HSTL18 class II HSTL18 class III -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35VCCIO 0.35VCCIO 0.42 0.35VCC 0.3VCCIO VREF - 0.2 VREF - 0.2 VREF - 0.18 VREF - 0.18 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 0.65VCCIO 0.65VCCIO 0.78 0.65VCC 0.5VCCIO VREF + 0.2 VREF + 0.2 VREF + 0.18 VREF + 0.18 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.4 0.2 0.4 0.2 0.4 0.2 0.1VCCIO 0.7 0.5 0.54 0.35 0.4 0.4 0.4 0.4 0.4 0.4 VOH Min. (V) VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 0.9VCCIO VCCIO - 1.1 VCCIO - 0.9 VCCIO - 0.62 VCCIO - 0.43 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 IOL (mA) 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 16, 12, 8, 4 0.1 8, 4 0.1 6, 2 0.1 6, 2 0.1 1.5 8 16 7.6 15.2 6.7 8 24 9.6 16 24 IOH (mA) -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -16, -12, -8, -4 -0.1 -8, -4 -0.1 -6, -2 -0.1 -6, -2 -0.1 -0.5 -8 -16 -7.6 -15.2 -6.7 -8 -8 -9.6 -16 -8 VREF - 0.125 VREF + 0.125 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-8 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet sysIO Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter Symbol VINP, VINM VTHD VCM IIN VOH VOL VOD VOD VOS VOS IOSD Parameter Description Input Voltage Differential Input Threshold 100mV VTHD Input Common Mode Voltage Input current Output high voltage for VOP or VOM Output low voltage for VOP or VOM Output voltage differential Change in VOD between high and low Output voltage offset Change in VOS between H and L Output short circuit current VOD = 0V Driver outputs shorted (VOP - VOM)/2, RT = 100 ohms 200mV VTHD 350mV VTHD Power on or power off RT = 100 ohms RT = 100 ohms (VOP - VOM), RT = 100 ohms Test Conditions Min. 0 +/-100 VTHD/2 VTHD/2 VTHD/2 -- -- 0.9V 250 -- 1.125 -- -- Typ. -- -- 1.2 1.2 1.2 -- 1.38 1.03 350 -- 1.25 -- -- Max. 2.4 -- 1.8 1.9 2.0 +/-10 1.60 -- 450 50 1.375 50 6 Units V mV V V V A V V mV mV V mV mA 3-9 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeXP devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example Bourns CAT16-LV4F12 VCCIO = 2.5V (5%) RS=165 ohms (1%) VCCIO = 2.5V (5%) RS=165 ohms (1%) RD = 140 ohms (1%) RD = 100 ohms (1%) + - Transmission line, Zo = 100 ohm differential ON-chip OFF-chip OFF-chip ON-chip Table 3-1. LVDS25E DC Conditions Over Recommended Operating Conditions Parameter VOH VOL VOD VCM ZBACK IDC Description Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 1.43 1.07 0.35 1.25 100 3.66 Units V V V V mA BLVDS The LatticeXP devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multidrop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. 3-10 Lattice Semiconductor Figure 3-2. BLVDS Multi-point Output Example DC and Switching Characteristics LatticeXP Family Data Sheet Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 80 45-90 ohms 45-90 ohms 80 2.5V 80 80 + 80 80 80 + 2.5V 2.5V ... 2.5V 2.5V - 2.5V 2.5V - + Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Symbol ZOUT RTLEFT RTRIGHT VOH VOL VOD VCM IDC Description Output impedance Left end termination Right end termination Output high voltage Output low voltage Output differential voltage Output common mode voltage DC output current Zo = 45 100 45 45 1.375 1.125 0.25 1.25 11.2 Zo = 90 100 90 90 1.48 1.02 0.46 1.25 10.2 Units ohms ohms ohms V V V V mA 1. For input buffer, see LVDS table. 3-11 + Lattice Semiconductor LVPECL DC and Switching Characteristics LatticeXP Family Data Sheet The LatticeXP devices support differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for pointto-point signals. Figure 3-3. Differential LVPECL 3.3V RS = 100 ohms 3.3V RS = 100 ohms RP = 187 ohms RT = 100 ohms + - Transmission line, Zo = 100 ohm differential Off-chip Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions Symbol ZOUT RP RS RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver parallel resistor Driver series resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 100 187 100 100 2.03 1.27 0.76 1.65 85.7 12.7 Units ohms ohms ohms ohms V V V V ohms mA 1. For input buffer, see LVDS table. For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet. RSDS The LatticeXP devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. 3-12 Lattice Semiconductor Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V RS DC and Switching Characteristics LatticeXP Family Data Sheet Zo = 100 VCCIO = 2.5V RS + RP RT - On-chip Emulated RSDS Buffer Off-chip Table 3-4. RSDS DC Conditions Parameter ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver series resistor Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 20 300 121 100 1.35 1.15 0.20 1.25 101.5 3.66 Units ohms ohms ohms ohms V V V V ohms mA 3-13 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Typical Building Block Function Performance1 Pin-to-Pin Performance (LVCMOS25 12 mA Drive) Function Basic Functions 16-bit decoder 32-bit decoder 64-bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 6.1 7.3 8.2 4.9 5.3 5.7 6.3 ns ns ns ns ns ns ns -5 Timing Units Register to Register Performance Function Basic Functions 16-bit decoder 32-bit decoder 64-bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 8-bit adder 16-bit adder 64-bit adder 16-bit counter 32-bit counter 64-bit counter 64-bit accumulator Embedded Memory Functions Single Port RAM 256x36 bits True-Dual Port RAM 512x18 bits Distributed Memory Functions 16x2 SP RAM 64x2 SP RAM 128x4 SP RAM 32x2 PDP RAM 64x4 PDP RAM 434 332 235 322 291 MHz MHz MHz MHz MHz 254 254 MHz MHz 351 248 237 590 523 434 355 343 292 130 388 295 200 164 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz -5 Timing Units 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v.F0.11 3-14 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Derating Logic Timing Logic timing provided in the following sections of this data sheet and in the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process can be much better than the values given in the tables. The ispLEVER design tool from Lattice can provide logic timing numbers at a particular temperature and voltage. 3-15 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP External Switching Characteristics Over Recommended Operating Conditions -5 Parameter Description Device LFXP3 LFXP6 tCO Clock to Output - PIO Output Register LFXP10 LFXP15 LFXP20 LFXP3 LFXP6 tSU Clock to Data Setup - PIO Input Register LFXP10 LFXP15 LFXP20 LFXP3 LFXP6 tH Clock to Data Hold - PIO Input Register LFXP10 LFXP15 LFXP20 LFXP3 LFXP6 tSU_DEL Clock to Data Setup - PIO Input Register with Input Data Delay LFXP10 LFXP15 LFXP20 LFXP3 tH_DEL LFXP6 Clock to Data Hold - PIO Input Register with LFXP10 Input Data Delay LFXP15 LFXP20 fMAX_IO tDVADQ tDVEDQ tDQVBS tDQVAS fMAX_DDR fMAX_PRI tW_PRI Clock Frequency of I/O and PFU Register Data Valid After DQS (DDR Read) Data Hold After DQS (DDR Read) Data Valid Before DQS Data Valid After DQS DDR Clock Frequency Frequency for Primary Clock Tree Clock Pulse Width for Primary Clock All All All All All All All All LFXP3/6/10/15 LFXP20 DDR I/O Pin Parameters2 -- 0.67 0.20 0.20 95 -- 1.19 -- -- 0.19 -- -- -- 166 450 -- 250 300 -- 0.67 0.20 0.20 95 -- 1.19 -- -- 0.19 -- -- -- 133 412 -- 300 350 -- 0.67 0.20 0.20 95 -- 1.19 -- -- 0.19 -- -- -- 100 375 -- 350 400 UI UI UI UI MHz MHz ns ps ps Min. -- -- -- -- -- -0.40 -0.33 -0.61 -0.71 -0.95 2.10 2.28 3.02 2.70 2.95 2.38 2.92 2.72 2.99 4.47 -0.70 -0.47 -0.60 -1.05 -0.80 -- Max. 5.12 5.30 5.52 5.72 5.97 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 400 Min. -- -- -- -- -- -0.28 -0.32 -0.71 -0.77 -1.14 2.50 2.72 3.51 3.22 3.52 2.49 3.18 2.75 3.13 4.56 -0.80 -0.38 -0.47 -0.98 -0.58 -- General I/O Pin Parameters (Using Primary Clock without PLL)1 6.12 6.34 6.60 6.84 7.14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 360 -- -- -- -- -- -0.16 -0.30 -0.81 -0.87 -1.35 2.98 3.24 3.71 3.85 4.21 2.66 3.42 2.84 3.18 4.80 -0.92 -0.31 -0.32 -1.01 -0.31 -- 7.43 7.69 8.00 8.29 8.65 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz -4 Max. Min. -3 Max. Units Primary and Secondary Clocks tSKEW_PRI Primary Clock Skew within an I/O Bank 1. General timing numbers based on LVCMOS 2.5, 12mA. 2. DDR timing numbers based on SSTL I/O. Timing v.F0.11 3-16 Lattice Semiconductor Figure 3-5. DDR Timings DQ and DQS Read Timings DQS DC and Switching Characteristics LatticeXP Family Data Sheet DQ tDVADQ tDVEDQ DQ and DQS Write Timings DQS DQ tDQVBS tDQVAS 3-17 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP Internal Timing Parameters1 Over Recommended Operating Conditions -5 Parameter PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU tLE2Q_PFU tLD2Q_PFU tCORAM_PFU tSUDATA_PFU tHDATA_PFU tSUADDR_PFU tHADDR_PFU tSUWREN_PFU tHWREN_PFU PIC Timing PIO Input/Output Buffer Timing tIN_PIO tOUT_PIO tSUI_PIO tHI_PIO tCOO_PIO tSUCE_PIO tHCE_PIO tSULSR_PIO tHLSR_PIO EBR Timing tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR tHWREN_EBR tSUCE_EBR tHCE_EBR Clock to Output from Address or Data Clock to Output from EBR Output Register Setup Data to EBR Memory Hold Data to EBR Memory Setup Address to EBR Memory Hold Address to EBR Memory Setup Write/Read Enable to EBR Memory Hold Write/Read Enable to EBR Memory Clock Enable Setup Time to EBR Output Register Clock Enable Hold Time to EBR Output Register -- -- -0.26 0.41 -0.26 0.41 -0.17 0.26 0.19 -0.13 4.01 0.81 -- -- -- -- -- -- -- -- -- -- -0.21 0.49 -0.21 0.49 -0.13 0.31 0.23 -0.10 4.81 0.97 -- -- -- -- -- -- -- -- -- -- -0.17 0.59 -0.17 0.59 -0.11 0.37 0.28 -0.08 5.78 1.17 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns Input Buffer Delay Output Buffer Delay Input Register Setup Time (Data Before Clock) Input Register Hold Time (Data After Clock) Output Register Clock to Output Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Set/Reset Setup Time Set/Reset Hold Time -- -- 1.35 0.05 -- -0.09 0.13 0.19 -0.14 0.62 2.12 -- -- 0.36 -- -- -- -- -- -- 1.83 0.05 -- -0.07 0.16 0.23 -0.11 0.72 2.54 -- -- 0.44 -- -- -- -- -- -- 2.37 0.05 -- -0.06 0.19 0.28 -0.09 0.85 3.05 -- -- 0.52 -- -- -- -- ns ns ns ns ns ns ns ns ns LUT4 Delay (A to D Inputs to F Output) LUT6 Delay (A to D Inputs to OFX Output) Set/Reset to Output of PFU Clock to Mux (M0,M1) Input Setup Time Clock to Mux (M0,M1) Input Hold Time Clock to D Input Setup Time Clock to D Input Hold Time Clock to Q Delay, D-type Register Configuration Clock to Q Delay Latch Configuration D to Q Throughput Delay when Latch is Enabled Clock to Output Data Setup Time Data Hold Time Address Setup Time Address Hold Time Write/Read Enable Setup Time Write/Read Enable Hold Time -- -- -- 0.13 -0.04 0.13 -0.03 -- -- -- -- -0.18 0.28 -0.46 0.71 -0.22 0.33 0.28 0.44 0.90 -- -- -- -- 0.40 0.53 0.55 0.40 -- -- -- -- -- -- -- -- -- 0.15 -0.03 0.16 -0.02 -- -- -- -- -0.14 0.34 -0.37 0.85 -0.17 0.40 0.34 0.53 1.08 -- -- -- -- 0.48 0.64 0.66 0.48 -- -- -- -- -- -- -- -- -- 0.19 -0.03 0.19 -0.02 -- -- -- -- -0.11 0.40 -0.30 1.02 -0.14 0.48 0.40 0.63 1.29 -- -- -- -- 0.58 0.76 0.79 0.58 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -4 Max. Min. -3 Max. Units PFU Dual Port Memory Mode Timing IOLOGIC Input/Output Timing 3-18 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP Internal Timing Parameters1 (Continued) Over Recommended Operating Conditions -5 Parameter tRSTO_EBR PLL Parameters tRSTREC tRSTSU Reset Recovery to Rising Clock Reset Signal Setup Time 1.00 1.00 -- -- 1.00 1.00 -- -- 1.00 1.00 -- -- ns ns Description Reset To Output Delay Time from EBR Output Register Min. -- Max. 1.61 Min. -- -4 Max. 1.94 Min. -- -3 Max. 2.32 Units ns 1. Internal parameters are characterized but not tested on every device. Timing v.F0.11 3-19 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing CK WRE AD[3:0] AD DI[1:0] D DO[1:0] Old Data D Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] AD DO[1:0] Old Data D 3-20 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet EBR Memory Timing Diagrams Figure 3-8. Read Mode (Normal) CLKA CSA WEA ADA A0 tSU tH A1 A0 A1 A0 DIA D0 D1 tACCESS tACCESS D1 D0 DOA D0 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. Figure 3-9. Read Mode with Input and Output Registers CLKA CSA WEA ADA A0 A1 A0 A1 A0 tSU tH DIA D0 D1 DOA Mem(n) data from previous read DOA D0 tACCESS D1 D0 tACCESS DOA (Registered) Mem(n) data from previous read output is only updated during a read cycle D0 D1 3-21 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA tSU A0 tH A1 A0 A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 tACCESS D1 tACCESS DOA old A0 Data old A1 Data D0 D1 D2 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU tH A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 D4 tACCESS DOA Data from Prev Read or Write D0 D1 D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. 3-22 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP Family Timing Adders1 Over Recommended Operating Conditions Buffer Type Input Adjusters LVDS25E LVDS25 BLVDS25 LVPECL33 HSTL18_I HSTL18_II HSTL18_III HSTL18D_I HSTL18D_II HSTL18D_III HSTL15_I HSTL15_III HSTL15D_I HSTL15D_III SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18D_I LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 Output Adjusters LVDS25E LVDS25 BLVDS25 LVPECL33 HSTL18_I HSTL18_II HSTL18_III HSTL18D_I HSTL18D_II HSTL18D_III LVDS 2.5 Emulated LVDS 2.5 BLVDS 2.5 LVPECL 3.3 HSTL_18 class I HSTL_18 class II HSTL_18 class III Differential HSTL 18 class I Differential HSTL 18 class II Differential HSTL 18 class III 0.3 0.3 0.3 0.1 0.1 0.1 0.2 0.1 -0.1 0.2 0.3 0.3 0.3 0.1 0.1 0.1 0.2 0.1 -0.1 0.2 0.3 0.3 0.3 0.1 0.1 0.1 0.2 0.1 -0.1 0.2 ns ns ns ns ns ns ns ns ns ns LVDS 2.5 Emulated LVDS BLVDS LVPECL HSTL_18 class I HSTL_18 class II HSTL_18 class III Differential HSTL 18 class I Differential HSTL 18 class II Differential HSTL 18 class III HSTL_15 class I HSTL_15 class III Differential HSTL 15 class I Differential HSTL 15 class III SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_18 class I Differential SSTL_18 class I LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 PCI 0.5 0.4 0.5 0.6 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.6 0.6 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.2 0.2 0.0 0.1 0.1 0.1 0.2 0.5 0.4 0.5 0.6 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.6 0.6 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.2 0.2 0.0 0.1 0.1 0.1 0.2 0.5 0.4 0.5 0.6 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.6 0.6 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.2 0.2 0.0 0.1 0.1 0.1 0.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -5 -4 -3 Units 3-23 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP Family Timing Adders1 (Continued) Over Recommended Operating Conditions Buffer Type HSTL15_I HSTL15_III HSTL15D_I HSTL15D_III SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18D_I LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVTTL33_20mA LVCMOS33_2mA LVCMOS33_4mA LVCMOS33_8mA Description HSTL_15 class I HSTL_15 class III Differential HSTL 15 class I Differential HSTL 15 class III SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_1.8 class I Differential SSTL_1.8 class I LVTTL 4mA drive LVTTL 8mA drive LVTTL 12mA drive LVTTL 16mA drive LVTTL 20mA drive LVCMOS 3.3 2mA drive LVCMOS 3.3 4mA drive LVCMOS 3.3 8mA drive -5 0.2 0.2 0.2 0.2 0.1 0.3 0.1 0.3 -0.1 0.3 -0.1 0.3 0.1 0.1 0.8 0.5 0.3 0.4 0.3 0.8 0.8 0.5 0.3 0.4 0.3 0.7 0.7 0.4 0.0 0.2 0.4 0.6 0.6 0.4 0.2 0.2 0.6 0.6 0.2 0.4 0.4 0.3 -4 0.2 0.2 0.2 0.2 0.1 0.3 0.1 0.3 -0.1 0.3 -0.1 0.3 0.1 0.1 0.8 0.5 0.3 0.4 0.3 0.8 0.8 0.5 0.3 0.4 0.3 0.7 0.7 0.4 0.0 0.2 0.4 0.6 0.6 0.4 0.2 0.2 0.6 0.6 0.2 0.4 0.4 0.3 -3 0.2 0.2 0.2 0.2 0.1 0.3 0.1 0.3 -0.1 0.3 -0.1 0.3 0.1 0.1 0.8 0.5 0.3 0.4 0.3 0.8 0.8 0.5 0.3 0.4 0.3 0.7 0.7 0.4 0.0 0.2 0.4 0.6 0.6 0.4 0.2 0.2 0.6 0.6 0.2 0.4 0.4 0.3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVCMOS33_12mA LVCMOS 3.3 12mA drive LVCMOS33_16mA LVCMOS 3.3 16mA drive LVCMOS33_20mA LVCMOS 3.3 20mA drive LVCMOS25_2mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS 2.5 2mA drive LVCMOS 2.5 4mA drive LVCMOS 2.5 8mA drive LVCMOS25_12mA LVCMOS 2.5 12mA drive LVCMOS25_16mA LVCMOS 2.5 16mA drive LVCMOS25_20mA LVCMOS 2.5 20mA drive LVCMOS18_2mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS 1.8 2mA drive LVCMOS 1.8 4mA drive LVCMOS 1.8 8mA drive LVCMOS18_12mA LVCMOS 1.8 12mA drive LVCMOS18_16mA LVCMOS 1.8 16mA drive LVCMOS15_2mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA PCI33 LVCMOS 1.5 2mA drive LVCMOS 1.5 4mA drive LVCMOS 1.5 8mA drive LVCMOS 1.2 2mA drive LVCMOS 1.2 6mA drive PCI33 1. General timing numbers based on LVCMOS 2.5, 12mA. Timing v.F0.11 3-24 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter fIN fOUT fOUT2 fVCO fPFD tDT tPH 4 Descriptions Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency (CLKOK) PLL VCO Frequency Phase Detector Input Frequency Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Programmable Delay Unit Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time RST Pulse Width Conditions Min. 25 25 0.195 375 25 Typ. -- -- -- -- -- 50 -- -- -- -- -- -- 250 -- -- -- -- -- Max. 375 375 187.5 750 -- 55 0.05 +/- 125 0.02 +/- 200 -- 150 400 +/- 200 10 -- -- -- Units MHz MHz MHz MHz MHz % UI ps UIPP ps ns us ps ps ns ns ns ns AC Characteristics Default duty cycle elected3 fOUT 100MHz fOUT < 100MHz Divider ratio = integer At 90% or 10%3 45 -- -- -- -- 1 -- 100 -- -- 90% to 90% 10% to 10% 0.5 0.5 10 tOPJIT1 tSK tW tLOCK2 tPA tIPJIT tFBKDLY tHI tLO tRST 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. As compared to CLKOP output. Timing v.F0.11 LatticeXP "C" Sleep Mode Timing Parameter tPWRDN Descriptions SLEEPN Low to I/O Tristate LFXP3 LFXP6 tPWRUP SLEEPN High to Power Up LFXP10 LFXP15 LFXP20 tWSLEEPN tWAWAKE SLEEPN Pulse Width to Initiate Sleep Mode SLEEPN Pulse Rejection Min. -- -- -- -- -- -- 400 -- Typ. 20 1.4 1.7 1.1 1.4 1.7 -- -- Max. 32 2.1 2.4 1.8 2.1 2.4 -- 120 Units ns ms ms ms ms ms ns ns Sleep Mode I/O tPWRUP tPWRDN SLEEPN 3-25 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet LatticeXP sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter sysCONFIG Byte Data Flow tSUCBDI tHCBDI tCODO tSUCS tHCS tSUWD tHWD tDCB tCORD tBSCH tBSCL tBSCYC tSUSCDI tHSCDI tCODO tSSCH tSSCL tICFG tVMC tPRGMRJ tPRGM2 tDINIT tDPPINIT tDINITD tIODISS tIOENSS tMWC Byte D[0:7] Setup Time to CCLK Byte D[0:7] Hold Time to CCLK Clock to Dout in Flowthrough Mode CS[0:1] Setup Time to CCLK CS[0:1] Hold Time to CCLK Write Signal Setup Time to CCLK Write Signal Hold Time to CCLK CCLK to BUSY Delay Time Clock to Out for Read Data Byte Slave Clock Minimum High Pulse Byte Slave Clock Minimum Low Pulse Byte Slave Clock Cycle Time DI (Data In) Setup Time to CCLK DI (Data In) Hold Time to CCLK Clock to Dout in Flowthrough Mode Serial Slave Clock Minimum High Pulse Serial Slave Clock Minimum Low Pulse Minimum Vcc to INIT High Time from tICFG to Valid Master Clock Program Pin Pulse Rejection PROGRAMN Low Time to Start Configuration INIT Low Time Delay Time from PROGRAMN Low to INIT Low Delay Time from PROGRAMN Low to DONE Low User I/O Disable from PROGRAMN Low User I/O Enabled Time from CCLK Edge During Wake-up Sequence Additional Wake Master Clock Signals after Done Pin High 7 3 -- 7 2 7 2 -- -- 6 8 15 7 2 -- 6 6 -- -- -- 25 -- -- -- -- -- 120 -- -- 12 -- -- -- -- 12 12 -- -- -- -- -- 12 -- -- 50 2 7 -- 1 37 37 25 25 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms us ns ns ms ns ns ns ns cycles Description Min. Max. Units sysCONFIG Byte Slave Clocking sysCONFIG Serial (Bit) Data Flow sysCONFIG Serial Slave Clocking sysCONFIG POR, Initialization and Wake Up Configuration Master Clock (CCLK) Frequency1 Duty Cycle Selected Selected Value Value + 30% 30% 40 60 MHz % 1. See Table 2-10 for available CCLK frequencies. 2. The threshold level for PROGRAMN, as well as for CFG[1] and CFG[0], is determined by VCC, such that the threshold = VCC/2. Timing v.F0.11 3-26 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Flash Download Time Symbol Parameter LFXP3 tREFRESH LFXP6 PROGRAMN Low-toHigh. Transition to Done LFXP10 High. LFXP15 LFXP20 Min. -- -- -- -- -- Typ. 1.1 1.4 0.9 1.1 1.3 Max. 1.7 2.0 1.5 1.7 1.9 Units ms ms ms ms ms JTAG Port Timing Specifications Over Recommended Operating Conditions Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Timing v.F0.11 Parameter TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Min. -- 40 20 20 10 8 50 -- -- -- 8 25 -- -- -- Max. 25 -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 3-12. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH TCK tBTCPL tBTH tBTCP tBTCOEN TDO Valid Data tBTCO Valid Data tBTCODIS tBTCRS Data to be captured from I/O tBTUPOEN Data to be driven out to I/O tBTCRH Data Captured tBUTCO Valid Data tBTUODIS Valid Data 3-27 Lattice Semiconductor DC and Switching Characteristics LatticeXP Family Data Sheet Switching Test Conditions Figure 3-13 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT CL Test Poi nt Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Test Condition R1 CL Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCIO/2 LVTTL and other LVCMOS settings (L -> H, H -> L) VT -- -- -- -- -- VOL VOH VOL VOH 0pF LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 188 0pF VCCIO/2 VCCIO/2 VOH - 0.15 VOL + 0.15 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-28 LatticeXP Family Data Sheet Pinout Information November 2007 Data Sheet DS1001 Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user programmable pins are shared with special function pins. These pin when not used as special purpose pins can be programmed as I/Os for user logic. During configuration, the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN NC GND VCC VCCAUX VCCP0 VCCP1 GNDP0 GNDP1 VCCIOx VREF1(x), VREF2(x) I -- -- -- -- -- -- -- -- -- -- Global RESET signal. (Active low). Any I/O pin can be configured to be GSRN. No connect. GND - Ground. Dedicated Pins. VCC - The power supply pins for core logic. Dedicated Pins. VCCAUX - The Auxiliary power supply pin. It powers all the differential and referenced input buffers. Dedicated Pins. Voltage supply pins for ULM0PLL (and LLM1PLL1). Voltage supply pins for URM0PLL (and LRM1PLL1). Ground pins for ULM0PLL (and LLM1PLL1). Ground pins for URM0PLL (and LRM1PLL1). VCCIO - The power supply pins for I/O bank x. Dedicated Pins. Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. Reference clock (PLL) input Pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A, B, C...at each side. Optional feedback (PLL) input Pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A, B, C...at each side. Primary Clock Pads, T = true and C = complement, n per side, indexed by bank and 0,1, 2, 3 within bank. DQS input Pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = Ball function number. Any pad can be configured to be DQS output. I/O Descriptions PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) [LOC][num]_PLL[T, C]_IN_A [LOC][num]_PLL[T, C]_FB_A PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] -- -- -- -- (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1001 Pinouts_02.5 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet Signal Descriptions (Cont.) Signal Name TMS TCK I/O I I Descriptions Test Mode Select input, used to control the 1149.1 state machine. Test Clock input pin, used to clock the 1149.1 state machine. Test Data in pin, used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Output pin -Test Data out pin used to shift data out of device using 1149.1. VCCJ - The power supply pin for JTAG Test Access Port. Mode pins used to specify configuration modes values latched on rising edge of INITN. During configuration, a pull-up is enabled. Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.) TDI I TDO VCCJ O -- Configuration Pads (used during sysCONFIG) CFG[1:0] INITN PROGRAMN DONE CCLK BUSY CSN CS1N WRITEN D[7:0] DOUT, CSON DI I Open Drain pin - Indicates the FPGA is ready to be configured. During conI/O figuration, a pull-up is enabled. If CFG1 and CFG0 are high (SDM) then this pin is pulled low. I I/O Initiates configuration sequence when asserted low. This pin always has an active pull-up. Open Drain pin - Indicates that the configuration sequence is complete, and the startup sequence is in progress. I/O Configuration Clock for configuring an FPGA in sysCONFIG mode. I/O Generally not used. After configuration it is a user-programmable I/O pin. I I I I/O O I sysCONFIG chip select (Active low). During configuration, a pull-up is enabled. After configuration it is user a programmable I/O pin. sysCONFIG chip select (Active Low). During configuration, a pull-up is enabled. After configuration it is user programmable I/O pin Write Data on Parallel port (Active low). After configuration it is a user programmable I/O pin sysCONFIG Port Data I/O. After configuration these are user programmable I/O pins. Output for serial configuration data (rising edge of CCLK) when using sysCONFIG port. After configuration, it is a user-programmable I/O pin. Input for serial configuration data (clocked with CCLK) when using sysCONFIG port. During configuration, a pull-up is enabled. After configuration it is a user-programmable I/O pin. Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates normally. When driven low, the device moves into Sleep Mode after a specified time.This pin has a weak internal pull-up, but when not used an external pull-up to VCC is recommended. Test Output Enable tri-states all I/O pins when driven low. This pin has a weak internal pull-up, but when not used an external pull-up to VCC is recommended. SLEEPN 2 I TOE3 1. Applies to LFXP10, LFXP15 and LFXP20 only. 2. Applies to LFXP "C" devices only. 3. Applies to LFXP "E" devices only. I 4-2 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] PIO within PIC A B A B A B A Polarity True Complement True Complement True Complement True DDR Strobe (DQS) and Data (DQ) Pins DQ DQ DQ DQ DQ DQ DQ B A B A B A B Complement True Complement True Complement True Complement DQ [Edge]DQSn DQ DQ DQ DQ DQ Notes: 1. "n" is a row/column PIC number. 2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. The definition of the PIC numbering is provided in the Signal Names column of the Signal Descriptions table in this data sheet. 4-3 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet Pin Information Summary1 XP3 Pin Type Single Ended User I/O Differential Pair User I/O Configuration TAP Dedicated (total without supplies) VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND GNDPLL NC Bank0 Bank1 Bank2 Single Ended/Differential Bank3 I/O per Bank2 Bank4 Bank5 Bank6 Bank7 VCCJ 2 XP6 208 PQFP 136 56 11 14 5 6 8 2 2 2 2 2 2 2 2 2 2 24 2 6 20/8 18/6 14/6 14/6 21/9 21/9 14/6 14/6 1 144 TQFP 100 35 11 14 5 6 4 2 2 1 1 1 1 2 1 1 1 13 2 0 12/3 12/2 12/5 13/5 14/6 12/4 13/5 12/5 1 208 PQFP 256 fpBGA 142 58 11 14 5 6 8 2 2 2 2 2 2 2 2 2 2 24 2 0 20/8 18/6 17/7 14/6 21/9 21/9 17/7 14/6 1 188 80 11 14 5 6 8 4 2 2 2 2 2 2 2 2 2 24 2 0 26/11 26/11 21/9 21/9 26/11 26/11 21/9 21/9 1 100 TQFP 62 19 144 TQFP 100 35 11 14 5 6 4 2 2 1 1 1 1 2 1 1 1 13 2 0 12/3 12/2 12/5 13/5 14/6 12/4 13/5 12/5 1 Dedicated Muxed 11 14 5 6 2 2 2 1 1 1 1 1 1 1 1 10 2 0 8/2 9/0 8/3 6/2 5/2 12/4 4/2 10/4 1 1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for more information. 4-4 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet Pin Information Summary1 (Cont.) XP10 Pin Type Single Ended User I/O Differential Pair User I/O Configuration TAP Dedicated (total without supplies) VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND GNDPLL NC Bank0 Bank1 Bank2 Single Ended/ Bank3 Differential I/O Bank4 per Bank2 Bank5 Bank6 Bank7 VCCJ Muxed 2 XP15 244 104 11 14 5 6 14 4 2 5 5 4 4 5 5 4 4 50 2 24 33/14 33/14 28/12 28/12 33/14 33/14 28/12 28/12 1 188 76 11 14 5 6 8 4 2 2 2 2 2 2 2 2 2 24 2 0 26/11 26/11 21/8 21/8 26/11 26/11 21/8 21/8 1 268 112 11 14 5 6 14 4 2 5 5 4 4 5 5 4 4 50 2 0 39/16 39/16 28/12 28/12 39/16 39/16 28/12 28/12 1 300 128 11 14 5 6 28 12 2 4 4 4 4 4 4 4 4 56 2 40 40/17 40/17 35/15 35/15 40/17 40/17 35/15 35/15 1 188 76 11 14 5 6 8 4 2 2 2 2 2 2 2 2 2 24 2 0 26/11 26/11 21/8 21/8 26/11 26/11 21/8 21/8 1 XP20 268 112 11 14 5 6 14 4 2 5 5 4 4 5 5 4 4 50 2 0 39/16 39/16 28/12 28/12 39/16 39/16 28/12 28/12 1 340 144 11 14 5 6 28 12 2 4 4 4 4 4 4 4 4 56 2 0 47/20 47/20 38/16 38/16 47/20 47/20 38/16 38/16 1 256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 188 76 11 14 5 6 8 4 2 2 2 2 2 2 2 2 2 24 2 0 26/11 26/11 21/8 21/8 26/11 26/11 21/8 21/8 1 Dedicated 1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for more information. 4-5 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet Power Supply and NC Connections Signals VCC 100 TQFP 28, 77 144 TQFP 14, 39, 73, 112 208 PQFP 256 fpBGA 388 fpBGA H9, J8, J15, K8, K15, L8, L15, M8, M15, N8, N15, P8, P15, R9 484 fpBGA F10, F13, G9, G10, G13, G14, H8, H15, J7, J16, K6, K7, K16, K17, N6, N7, N16, N17, P7, P16, R8, R15, T9, T10, T13, T14, U10, U13 19, 35, 53, 80, 107, D4, D13, E5, E12, 151, 158, 182 M5, M12, N4, N13 VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJ VCCP0 VCCP1 VCCAUX 94 82 65 58 47 38 22 7 73 17 60 25, 71 133 119 98 88 61, 68 49 21 8 108 19 91 36, 106 189, 199 167, 177 140, 149 115, 125 87, 97 64, 74 28, 41 13, 23 154 25 128 50, 152 F7, F8 F9, F10 G11, H11 J11, K11 L9, L10 L7, L8 J6, K6 G6, H6 D16 H4 J12 E4, E13, M4, M13 G8, G9, G10, G11, F11, G11, H10, H8 H11 G12, G13, G14, G15, H15 M16, N16, P16, R16 R15, T12, T13, T14, T15 R8, T8, T9, T10, T11 M7, N7, P7, R7 H7, J7, K7, L7 E20 M2 M21 G7, G16, T7, T16 F12, G12, H12, H13 M15, M16, M17, N15 R12, R13, T12, U12 R10, R11, T11, U11 M6, M7, M8, N8 K8, L6, L7, L8 E20 L5 L18 G7, G8, G15, G16, H7, H16, R7, R16, T7, T8, T15, T16 A1, A2, A21, A22, B1, B22, H9, H14, J8, J9, J10, J11, J12, J13, J14, J15, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, M20, N2, N9, N10, N11, N12, N13, N14, P8, P9, P10, P11, P12, P13, P14, P15, R9, R14, AA1, AA22, AB1, AB2, AB21, AB22 XP15: B21, C4, C5, C6, C18, C19, C20, C21, D6, D18, E4, E6, E18, F6, L1, L19, L20, M1, M2, M19, M21, N1, N21, N22, P1, P2, U5, U6, U17, U18, V5, V6, V17, V18, W17, W18, W19, Y3, Y4, Y5 H16, J16, K16, L16 K15, L15, L16, L17 GND1 10, 18, 21, 33, 43, 44, 52, 59, 68, 84, 90, 99 3, 11, 20, 28, 44, 54, 56, 64, 75, 85, 90, 101, 121, 127, 136 5, 7, 16, 26, 38, 47, 49, 59, 69, 79, 82, 92, 106, 109, 118, 121, 127, 130, 135, 143, 163, 172, 181, 184, 194, 207 A1, A16, F6, F11, G7, G8, G9, G10, H5, H7, H8, H9, H10, J7, J8, J9, J10, J13, K7, K8, K9, K10, L6, L11, T1, T16 A1, A22, H10, H11, H12, H13, H14, J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N1, N9, N10, N11, N12, N13, N14, N22, P9, P10, P11, P12, P13, P14, R10, R11, R12, R13, R14, AB1, AB22 XP10: C2, C15, C16, C17, D4, D5, D6, D7, D16, D17, E4, E19, W3, W4, W7, W17, W18, W19, W20, Y3, Y15, Y16, AA1, AA2 NC2 -- -- XP3: 27, 33, 34, 129, 133, 134 -- 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 4-6 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 Logic Signal Connections: 100 TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin Function CFG1 DONE PROGRAMN CCLK PL3A PL3B VCCIO7 PL5A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL9B VCCP0 GNDP0 PL12A PL12B GNDIO6 VCCIO6 PL18A PL18B VCCAUX SLEEPN1/TOE2 INITN VCC PB2B PB5B PB8A PB8B GNDIO5 PB9A PB10B PB11A PB11B VCCIO5 PB12A PB12B PB13A PB13B GND Bank 0 0 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Differential T C T 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 VREF2_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A PCLKT6_0 PCLKC6_0 VREF1_5 VREF2_5 DQS - C3 T C T3 C3 T C T 3 C3 T C T C T C T C - 4-7 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 Logic Signal Connections: 100 TQFP (Cont.) Pin Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin Function GNDIO4 PB15A PB15B VCCIO4 PB19A PB19B PB24A PR18B GNDIO3 PR18A PR15B PR14A PR13B PR13A VCCIO3 GNDP1 VCCP1 PR9B PR9A PR8B PR8A VCCIO2 PR6B PR5A GNDIO2 PR3B PR3A VCCAUX TDO VCCJ TDI TMS TCK VCC PT24A PT23A PT22B PT21A VCCIO1 PT20B GNDIO1 PT17A PT16A PT15B Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Differential T C T C C3 T 3 Dual Function PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 VREF1_3 VREF2_3 PCLKC2_0 PCLKT2_0 RUM0_PLLC_IN_A RUM0_PLLT_IN_A VREF1_2 VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A D0 D1 D2 D3 D4 D5 D6 C T C T C T C T - 4-8 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 Logic Signal Connections: 100 TQFP (Cont.) Pin Number 88 89 90 91 92 93 94 95 96 97 98 99 100 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. Pin Function PT14B PT13B GNDIO0 PT13A PT12B PT12A VCCIO0 PT9A PT8A PT6A PT5A GND CFG0 Bank 1 0 0 0 0 0 0 0 0 0 0 0 Differential C T C T - Dual Function D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DOUT WRITEN DI CSN - 4-9 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 LFXP3 Pin Function PROGRAMN CCLK GND PL2A PL2B PL3A PL3B VCCIO7 PL5A PL6B GNDIO7 PL7A PL7B VCC PL8A PL8B PL9A PL9B VCCP0 GNDP0 VCCIO6 PL11A PL11B PL12A PL12B PL13A PL13B GNDIO6 PL14A PL15B PL16A PL16B PL17A PL18A PL18B VCCAUX SLEEPN1/TOE2 INITN VCC PB2B PB5B PB7A PB7B GNDIO5 PB9A PB10B Bank 7 7 Differential T3 C3 T C T3 C3 T C T3 C T3 C 3 3 LFXP6 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 VREF2_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A PCLKT6_0 PCLKC6_0 VREF1_6 VREF2_6 DQS VREF1_5 VREF2_5 Pin Function PROGRAMN CCLK GND PL2A PL2B PL3A PL3B VCCIO7 PL5A PL6B GNDIO7 PL7A PL7B VCC PL8A PL8B PL9A PL9B VCCP0 GNDP0 VCCIO6 PL16A PL16B PL17A PL17B PL18A PL18B GNDIO6 PL22A PL23B PL24A PL24B PL25A PL26A PL26B VCCAUX SLEEPN1/TOE2 INITN VCC PB5B PB8B PB10A PB10B GNDIO5 PB12A PB13B Bank 7 7 Differential T3 C3 T C T3 C3 T C T3 C T3 C3 T C T 3 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 VREF2_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A PCLKT6_0 PCLKC6_0 VREF1_6 VREF2_6 DQS VREF1_5 VREF2_5 - 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 T C T 3 C3 T3 C3 C3 T3 C3 T3 C3 T C - T3 C 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C - 4-10 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 LFXP3 Pin Function PB11A PB11B VCCIO5 PB12A PB12B PB13A PB13B GND PB14A GNDIO4 PB14B PB15A PB15B PB16A VCCIO4 PB16B PB19A GNDIO4 PB19B PB20A PB20B VCCIO4 PB22A PB24A PB24B PB25A VCC PR18B GNDIO3 PR18A PR17B PR17A PR16B PR16A PR15B PR14A PR13B PR13A GND PR12A PR11B VCCIO3 PR11A GNDP1 VCCP1 PR9B Bank 5 5 5 5 5 5 5 Differential T C T C T C T C T C T C T C T C Dual Function DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS VREF1_3 VREF2_3 PCLKC2_0 Pin Function PB14A PB14B VCCIO5 PB15A PB15B PB16A PB16B GND PB17A GNDIO4 PB17B PB18A PB18B PB19A VCCIO4 PB19B PB22A GNDIO4 PB22B PB23A PB23B VCCIO4 PB25A PB27A PB27B PB28A VCC PR26B GNDIO3 PR26A PR25B PR25A PR24B PR24A PR23B PR22A PR21B PR21A GND PR20A PR19B VCCIO3 PR19A GNDP1 VCCP1 PR12B Bank 5 5 5 5 5 5 5 LFXP6 Differential T C T C T C T C T C T C T C T C T C C3 T3 C T C3 T3 C3 T3 C3 T3 C Dual Function DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS VREF1_3 VREF2_3 PCLKC2_0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 T C C3 T3 C T C3 T3 C T - 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 3 3 2 C T C 4-11 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 LFXP3 Pin Function PR9A PR8B PR8A PR7B PR7A VCCIO2 PR6B PR5A GNDIO2 PR3B PR3A PR2B PR2A VCCAUX TDO VCCJ TDI TMS TCK VCC PT25A PT24A PT23A PT22B PT22A PT21A VCCIO1 PT20B GNDIO1 PT17A PT16A PT15B PT15A PT14B GND PT13B PT13A PT12B PT12A PT11B VCCIO0 PT11A PT9A GNDIO0 PT8A PT7A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 Differential T C T C C T C 3 3 LFXP6 Dual Function PCLKT2_0 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF1_2 VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 D0 D1 VREF2_1 D2 D3 D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 Pin Function PR12A PR8B PR8A PR7B PR7A VCCIO2 PR6B PR5A GNDIO2 PR3B PR3A PR2B PR2A VCCAUX TDO VCCJ TDI TMS TCK VCC PT28A PT27A PT26A PT25B PT25A PT24A VCCIO1 PT23B GNDIO1 PT20A PT19A PT18B PT18A PT17B GND PT16B PT16A PT15B PT15A PT14B VCCIO0 PT14A PT12A GNDIO0 PT11A PT10A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 Differential T C T C C T C C T C T C T C T C T 3 3 Dual Function PCLKT2_0 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF1_2 VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 D0 D1 VREF2_1 D2 D3 D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 T3 T3 T3 T3 - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T - C T C T C T C T - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4-12 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number 139 140 141 142 143 144 LFXP3 Pin Function PT6A PT5A PT3B CFG0 CFG1 DONE Bank 0 0 0 0 0 0 Differential Dual Function DI CSN VREF2_0 Pin Function PT9A PT8A PT6B CFG0 CFG1 DONE Bank 0 0 0 0 0 0 LFXP6 Differential Dual Function DI CSN VREF2_0 - 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-13 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 LFXP3 Pin Function CFG1 DONE PROGRAMN CCLK GND PL2A GNDIO7 PL2B PL3A PL3B PL4A PL4B VCCIO7 PL5A PL6B GNDIO7 PL7A PL7B VCC PL8A PL8B PL9A VCCIO7 PL9B VCCP0 GNDP0 NC VCCIO6 PL11A PL11B PL12A PL12B NC NC VCC PL13A PL13B GNDIO6 PL14A PL15B VCCIO6 PL16A PL16B PL17A PL17B PL18A Bank 0 0 7 7 Differential T 3 LFXP6 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 VREF2_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A PCLKT6_0 PCLKC6_0 VREF1_6 VREF2_6 DQS Pin Function CFG1 DONE PROGRAMN CCLK GND PL2A GNDIO7 PL2B PL3A PL3B PL4A PL4B VCCIO7 PL5A PL6B GNDIO7 PL7A PL7B VCC PL8A PL8B PL9A VCCIO7 PL9B VCCP0 GNDP0 PL15B VCCIO6 PL16A PL16B PL17A PL17B PL18A PL18B VCC PL21A PL21B GNDIO6 PL22A PL23B VCCIO6 PL24A PL24B PL25A PL25B PL26A Bank 0 0 7 7 Differential T 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 VREF2_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A PCLKT6_0 PCLKC6_0 VREF1_6 VREF2_6 DQS - 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C 3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C 3 7 7 7 7 7 6 6 6 6 6 - 7 7 7 7 7 6 6 6 6 6 6 6 6 T C T3 C3 T 3 T C T3 C T3 C3 T 3 3 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C3 T C T 3 C3 T C T 3 4-14 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 LFXP3 Pin Function GNDIO6 PL18B GND VCCAUX SLEEPN1/TOE2 INITN VCC PB2B PB3A PB3B PB4A PB4B GNDIO5 PB5A PB5B PB6A PB6B VCCIO5 PB7A PB7B PB8A PB8B GNDIO5 PB9A PB10B PB11A PB11B VCCIO5 PB12A PB12B PB13A PB13B GND VCC PB14A GNDIO4 PB14B PB15A PB15B PB16A VCCIO4 PB16B PB17A PB18B PB19A GNDIO4 Bank 6 6 Differential C3 T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF1_5 VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS Pin Function GNDIO6 PL26B GND VCCAUX SLEEPN1/TOE2 INITN VCC PB5B PB6A PB6B PB7A PB7B GNDIO5 PB8A PB8B PB9A PB9B VCCIO5 PB10A PB10B PB11A PB11B GNDIO5 PB12A PB13B PB14A PB14B VCCIO5 PB15A PB15B PB16A PB16B GND VCC PB17A GNDIO4 PB17B PB18A PB18B PB19A VCCIO4 PB19B PB20A PB21B PB22A GNDIO4 Bank 6 6 LFXP6 Differential C3 T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF1_5 DQS VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS - 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4-15 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 LFXP3 Pin Function PB19B PB20A PB20B PB21A VCCIO4 PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A GND VCC PR18B GNDIO3 PR18A PR17B PR17A PR16B PR16A VCCIO3 PR15B PR14A GNDIO3 PR13B PR13A GND PR12B PR12A PR11B VCCIO3 PR11A GNDP1 VCCP1 NC GND PR9B PR9A NC NC GNDIO2 PR8B PR8A PR7B Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 Differential C T C T C T C T C T C C T3 C T C3 T3 C T C T C T C T C T C3 3 LFXP6 Dual Function VREF1_4 VREF2_4 DQS VREF1_3 VREF2_3 PCLKC2_0 PCLKT2_0 RUM0_PLLC_IN_A RUM0_PLLT_IN_A Pin Function PB22B PB23A PB23B PB24A VCCIO4 PB24B PB25A PB25B PB26A PB26B PB27A PB30A PB30B GND VCC PR26B GNDIO3 PR26A PR25B PR25A PR24B PR24A VCCIO3 PR23B PR22A GNDIO3 PR21B PR21A GND PR20B PR20A PR19B VCCIO3 PR19A GNDP1 VCCP1 PR13A GND PR12B PR12A PR11B PR11A GNDIO2 PR8B PR8A PR7B Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 Differential C T C T C T C T C T C C T3 C T C3 T3 C3 T 3 3 Dual Function VREF1_4 VREF2_4 DQS DQS VREF1_3 VREF2_3 PCLKC2_0 PCLKT2_0 RUM0_PLLC_IN_A RUM0_PLLT_IN_A - 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 - 3 3 3 3 3 2 C T C T3 C T C3 T3 C T C3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4-16 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 LFXP3 Pin Function PR7A VCCIO2 PR6B PR5A GNDIO2 PR4B PR4A PR3B PR3A PR2B VCCIO2 PR2A VCC VCCAUX TDO VCCJ TDI TMS TCK VCC PT25A PT24B PT24A PT23A GNDIO1 PT22B PT22A PT21A VCCIO1 PT20B PT20A PT19B PT19A GNDIO1 PT18B PT17A PT16B PT16A VCCIO1 PT15B PT15A PT14B GND VCC PT13B GNDIO0 Bank 2 2 2 2 2 2 2 2 2 2 2 2 Differential T3 C3 T3 C T C3 T3 C T C T C T C T C T C T C Dual Function DQS VREF1_2 VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY Pin Function PR7A VCCIO2 PR6B PR5A GNDIO2 PR4B PR4A PR3B PR3A PR2B VCCIO2 PR2A VCC VCCAUX TDO VCCJ TDI TMS TCK VCC PT28A PT27B PT27A PT26A GNDIO1 PT25B PT25A PT24A VCCIO1 PT23B PT23A PT22B PT22A GNDIO1 PT21B PT20A PT19B PT19A VCCIO1 PT18B PT18A PT17B GND VCC PT16B GNDIO0 Bank 2 2 2 2 2 2 2 2 2 2 2 2 LFXP6 Differential T3 C3 T3 C T C3 T3 C T C T C T C T C T C T C Dual Function DQS VREF1_2 VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 4-17 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 LFXP3 Pin Function PT13A PT12B PT12A PT11B VCCIO0 PT11A PT10B PT9A PT8B GNDIO0 PT8A PT7B PT7A PT6B VCCIO0 PT6A PT5B PT5A PT4B PT4A PT3B PT2B GND CFG0 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Differential T C T C T C T C T C T C T C T Dual Function CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 Pin Function PT16A PT15B PT15A PT14B VCCIO0 PT14A PT13B PT12A PT11B GNDIO0 PT11A PT10B PT10A PT9B VCCIO0 PT9A PT8B PT8A PT7B PT7A PT6B PT5B GND CFG0 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFXP6 Differential T C T C T C T C T C T C T C T Dual Function CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 - 0 0 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-18 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA LFXP6 Ball Number C2 C1 D2 D3 D1 E2 E1 F1 E3 F4 F3 F2 G1 G3 G2 H1 H2 G4 G5 J1 J2 H3 J3 H4 H5 K1 K2 J4 J5 L1 L2 M1 M2 K3 L3 L4 Ball Function PROGRAMN CCLK GNDIO7 PL3A PL3B PL2A PL5A GNDIO7 PL7A PL7B PL12A PL12B PL4A PL4B GNDIO7 PL2B PL8A PL8B PL9A PL9B PL6B PL14A GNDIO7 PL11A PL11B PL13A PL13B VCCP0 GNDP0 PL17A PL17B GNDIO6 PL15B PL22A PL16A PL16B PL18A PL18B PL19A GNDIO6 PL19B PL21A Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 T C T3 T 3 LFXP10 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 PCLKT6_0 PCLKC6_0 VREF1_6 Ball Function PROGRAMN CCLK GNDIO7 PL3A PL3B PL5A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL9B GNDIO7 PL11B PL12A PL12B PL13A PL13B PL14A PL15B GNDIO7 PL16A PL16B PL18A PL18B VCCP0 GNDP0 PL20A PL20B GNDIO6 PL22A PL23B PL24A PL24B PL25A PL25B PL26A GNDIO6 PL26B PL28A Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 T C T 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS LLM0_PLLT_IN_A LLM0_PLLC_IN_A - C3 T C T3 C C3 T C T3 C3 T3 C3 T 3 3 3 C3 T C T3 C3 T C T 3 C3 T3 C3 T3 C T C T3 C3 T C T3 C 3 3 C - T C T3 C T 3 3 C3 T3 C 3 T3 4-19 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number K4 K5 N1 N2 P1 P2 L5 M6 M3 N3 P4 P3 R4 N5 P5 R1 N6 M7 R2 T2 R3 T3 T4 R5 N7 M8 T5 P6 T6 R6 P7 N8 R7 T7 P8 T8 Ball Function PL20A PL20B GNDIO6 PL23B PL21B PL24A PL24B PL25A PL25B PL26A GNDIO6 PL26B SLEEPN1/TOE2 INITN GNDIO5 PB2A PB2B GNDIO5 PB5B PB3B PB4A PB3A PB6A PB6B PB7A PB7B GNDIO5 PB8A PB8B PB9A PB9B PB10A PB10B PB11A PB11B GNDIO5 PB12A PB13B PB14A PB14B PB15A PB15B Bank Differential 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C C3 T 3 LFXP10 Dual Function VREF2_6 DQS VREF1_5 DQS VREF2_5 DQS Ball Function PL29A PL29B GNDIO6 PL31A PL32B PL33A PL33B PL34A PL34B PL35A GNDIO6 PL35B SLEEPN1/TOE2 INITN GNDIO5 PB6A PB6B GNDIO5 PB7A PB7B PB8A PB9B PB10A PB10B PB11A PB11B GNDIO5 PB12A PB12B PB13A PB13B PB14A PB14B PB15A PB15B GNDIO5 PB16A PB17B PB18A PB18B PB19A PB19B Bank Differential 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T 3 Dual Function VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A VREF1_5 DQS VREF2_5 DQS - C3 T C T3 C3 T C C T T C T C T C T C T C T C T C T C C3 T C T3 C T C T C T C T C T C T C T C T C T C T C 3 4-20 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number R8 T9 R9 P9 T10 T11 R10 P10 N9 M9 R12 T12 P13 R13 M11 N11 N10 M10 T13 P14 R11 P12 T14 R14 P11 N12 T15 R15 P15 N15 P16 R16 M15 N14 M14 L13 Ball Function PB16A PB16B PB17A GNDIO4 PB17B PB18A PB18B PB19A PB19B PB20A PB21B PB22A GNDIO4 PB22B PB23A PB23B PB24A PB24B PB25A PB25B PB26A GNDIO4 PB26B PB27A PB27B PB28A PB29B PB30A PB30B PB31A GNDIO4 PB31B GNDIO3 PR26B PR26A PR24B PR24A PR15B PR23B GNDIO3 PR25B PR25A Bank Differential 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T C T C T C T C T C T C C C C T 3 LFXP10 Dual Function PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS DQS VREF1_3 Ball Function PB20A PB20B PB21A GNDIO4 PB21B PB22A PB22B PB23A PB23B PB24A PB25B PB26A GNDIO4 PB26B PB27A PB27B PB28A PB28B PB29A PB29B PB30A GNDIO4 PB30B PB31A PB31B PB32A PB33B PB34A PB34B PB35A GNDIO4 PB35B GNDIO3 PR34B PR34A PR33B PR33A PR32B PR31A GNDIO3 PR29B PR29A Bank Differential 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T C T C T C T C T C T C C T C C T 3 Dual Function PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 - T3 3 T3 T3 4-21 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number L15 L14 L12 M16 N16 K14 K15 K12 K13 L16 K16 J15 J14 J13 J12 J16 H16 H13 H12 H15 H14 G15 G14 G16 F16 G13 G12 F13 B16 C16 F15 E15 F14 E14 D15 C15 Ball Function PR21B PR21A GNDIO3 PR17B PR20B PR20A PR19B PR19A PR17A PR22A GNDIO3 PR18B PR18A PR16B PR16A GNDP1 VCCP1 GNDIO2 PR12B PR12A PR13B PR13A PR2B PR6B GNDIO2 PR11B PR11A PR8B PR8A PR2A GNDIO2 PR9B PR9A PR7B PR7A PR14A PR5A GNDIO2 PR4B PR4A PR3B PR3A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T 3 LFXP10 Dual Function VREF2_3 Ball Function PR28B PR28A GNDIO3 PR26A PR25B PR25A PR24B PR24A PR23B PR22A GNDIO3 PR21B PR21A PR19B PR19A GNDP1 VCCP1 GNDIO2 PR17B PR17A PR16B PR16A PR15B PR14A GNDIO2 PR13B PR13A PR12B PR12A PR11B GNDIO2 PR8B PR8A PR7B PR7A PR6B PR5A GNDIO2 PR4B PR4A PR3B PR3A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T 3 Dual Function RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 - C C T C3 T 3 C T C3 T 3 T C C C T C3 T 3 3 C C C T C3 T 3 3 PCLKC2_0 PCLKT2_0 VREF1_2 - PCLKC2_0 PCLKT2_0 DQS VREF1_2 - T3 3 T3 3 T3 T3 C3 C 3 C 3 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A T3 C T T 3 T3 C T C T C C3 T3 C T 3 C C C3 T3 C T 3 T3 3 T3 T3 4-22 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number E16 D16 D14 C14 B14 A15 B15 D12 C11 A14 B13 F12 E11 A13 C13 C10 E10 A12 B12 C12 A11 B11 D11 B9 D9 A10 B10 D10 A9 C9 C8 E9 B8 A8 A7 B7 C7 Ball Function TDO VCCJ TDI TMS TCK GNDIO1 PT31B PT31A GNDIO1 PT28A PT30A PT29B PT30B PT27B PT27A PT26B PT26A GNDIO1 PT25B PT25A PT24B PT24A PT23B PT23A PT22B PT22A GNDIO1 PT21B PT20A PT19B PT19A PT18B PT18A PT17B PT17A PT16B GNDIO0 PT16A PT15B PT15A PT14B PT14A Bank Differential 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 C T T C C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS Ball Function TDO VCCJ TDI TMS TCK GNDIO1 PT35B PT35A GNDIO1 PT34B PT34A PT33B PT32A PT31B PT31A PT30B PT30A GNDIO1 PT29B PT29A PT28B PT28A PT27B PT27A PT26B PT26A GNDIO1 PT25B PT24A PT23B PT23A PT22B PT22A PT21B PT21A PT20B GNDIO0 PT20A PT19B PT19A PT18B PT18A LFXP10 Bank Differential 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS 4-23 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number E8 D8 A6 C6 E7 D7 A5 B5 A4 B6 E6 D6 D5 A3 B3 B2 A2 B1 F5 C5 C4 B4 C3 A1 A16 F11 F6 G10 G7 G8 G9 H10 H7 H8 H9 J10 J7 J8 J9 Ball Function PT13B PT12A PT11B GNDIO0 PT11A PT10B PT10A PT9B PT9A PT8B PT8A PT7B GNDIO0 PT7A PT6B PT6A PT5B PT4A PT3B PT3A PT2B GNDIO0 PT2A CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Differential 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T Dual Function DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS Ball Function PT17B PT16A PT15B GNDIO0 PT15A PT14B PT14A PT13B PT13A PT12B PT12A PT11B GNDIO0 PT11A PT10B PT10A PT9B PT8A PT7B PT7A PT6B GNDIO0 PT6A CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFXP10 Bank Differential 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T Dual Function DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS - 4-24 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Number K10 K7 K8 K9 L11 L6 T1 T16 D13 D4 E12 E5 M12 M5 N13 N4 E13 E4 M13 M4 F7 F8 F10 F9 G11 H11 J11 K11 L10 L9 L7 L8 J6 K6 G6 H6 Ball Function GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 Bank Differential 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Dual Function Ball Function GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 LFXP10 Bank Differential 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Dual Function - 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-25 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA LFXP15 Ball Number C2 C1 D2 D3 D1 E2 E1 F1 E3 F4 F3 F2 G1 G3 G2 H1 H2 G4 G5 J1 J2 H3 J3 H4 H5 K1 K2 J4 J5 L1 L2 M1 M2 K3 L3 Ball Function PROGRAMN CCLK GNDIO7 GNDIO7 PL7A PL7B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL22A PL22B VCCP0 GNDP0 PL24A GNDIO6 PL24B PL26A PL27B PL28A PL28B GNDIO6 PL29A PL29B PL30A PL30B Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 T C T3 C T C T3 C3 T C T3 C T3 C3 T3 C T C T3 C T C T3 C 3 3 3 3 3 LFXP20 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS LLM0_PLLT_IN_A LLM0_PLLC_IN_A Ball Function PROGRAMN CCLK GNDIO7 GNDIO7 PL7A PL7B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL22A PL22B VCCP0 GNDP0 PL28A GNDIO6 PL28B PL30A PL31B PL32A PL32B GNDIO6 PL33A PL33B PL34A PL34B Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 T C T3 C3 T C T3 C3 T C T3 C T3 C3 T3 C3 T C T3 C T C T3 C3 3 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS LLM0_PLLT_IN_A LLM0_PLLC_IN_A - 4-26 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number L4 K4 K5 N1 N2 P1 P2 L5 M6 M3 N3 P4 P3 R4 N5 P5 R1 N6 M7 R2 T2 R3 T3 T4 R5 N7 M8 T5 P6 T6 R6 P7 N8 R7 Ball Function PL32A GNDIO6 PL33A PL33B PL35A PL36B PL37A PL37B GNDIO6 PL38A PL38B PL39A PL39B GNDIO6 SLEEPN1/TOE2 INITN GNDIO5 GNDIO5 GNDIO5 PB11A PB11B PB12A GNDIO5 PB12B PB13A PB14B PB15A PB15B PB16A PB16B PB17A PB17B PB18A GNDIO5 PB18B PB19A PB19B PB20A PB20B PB21A PB22B PB23A Bank Differential 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T3 C3 T C T3 C T C T C T C T C T C T C T C T C T 3 LFXP20 Dual Function VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A VREF1_5 DQS VREF2_5 DQS Ball Function PL36A GNDIO6 PL37A PL37B PL39A PL40B PL41A PL41B GNDIO6 PL42A PL42B PL43A PL43B GNDIO6 SLEEPN1/TOE2 INITN GNDIO5 GNDIO5 GNDIO5 PB15A PB15B PB16A GNDIO5 PB16B PB17A PB18B PB19A PB19B PB20A PB20B PB21A PB21B PB22A GNDIO5 PB22B PB23A PB23B PB24A PB24B PB25A PB26B PB27A Bank Differential 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T3 C3 T C T3 C3 T C T C T C T C T C T C T C T C T Dual Function VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A VREF1_5 DQS VREF2_5 DQS 4-27 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number T7 P8 T8 R8 T9 R9 P9 T10 T11 R10 P10 N9 M9 R12 T12 P13 R13 M11 N11 N10 M10 T13 P14 R11 P12 T14 R14 P11 N12 T15 R15 P15 N15 Ball Function PB23B GNDIO5 PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B GNDIO4 PB28A PB28B PB29A PB30B PB31A PB31B PB32A PB32B PB33A GNDIO4 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A PB38B GNDIO4 PB39A PB39B PB40A PB40B GNDIO4 GNDIO4 GNDIO4 GNDIO3 GNDIO3 PR38B PR38A Bank Differential 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 C T C T C T C T C T C T C T C T C T C T C T C T C T C C T Dual Function PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS RLM0_PLLC_FB_A RLM0_PLLT_FB_A Ball Function PB27B GNDIO5 PB28A PB28B PB29A PB29B PB30A PB30B PB31A PB31B GNDIO4 PB32A PB32B PB33A PB34B PB35A PB35B PB36A PB36B PB37A GNDIO4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A PB42B GNDIO4 PB43A PB43B PB44A PB44B GNDIO4 GNDIO4 GNDIO4 GNDIO3 GNDIO3 PR42B PR42A LFXP20 Bank Differential 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 C T C T C T C T C T C T C T C T C T C T C T C T C T C C T Dual Function PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS RLM0_PLLC_FB_A RLM0_PLLT_FB_A 4-28 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number P16 R16 M15 N14 M14 L13 L15 L14 L12 M16 N16 K14 K15 K12 K13 L16 K16 J15 J14 J13 J12 J16 H16 H13 H12 H15 H14 G15 G14 G16 F16 G13 G12 F13 B16 C16 Ball Function PR37B PR37A PR36B PR35A GNDIO3 PR33B PR33A PR32B PR32A PR30A PR29B PR29A GNDIO3 PR28B PR28A PR27B PR26A PR25B PR25A GNDIO3 PR23B PR23A GNDP1 VCCP1 GNDIO2 PR21B PR21A PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B GNDIO2 PR12B PR12A PR11B PR11A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T 3 LFXP20 Dual Function DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 PCLKC2_0 PCLKT2_0 DQS VREF1_2 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS Ball Function PR41B PR41A PR40B PR39A GNDIO3 PR37B PR37A PR36B PR36A PR34A PR33B PR33A GNDIO3 PR32B PR32A PR31B PR30A PR29B PR29A GNDIO3 PR27B PR27A GNDP1 VCCP1 GNDIO2 PR21B PR21A PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B GNDIO2 PR12B PR12A PR11B PR11A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T 3 Dual Function DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 PCLKC2_0 PCLKT2_0 DQS VREF1_2 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS C T C C T C C3 T 3 3 3 C T C C T C C3 T3 C3 T3 C T C3 T 3 3 3 T3 T3 T3 T3 C3 T3 C T C T C3 T3 C T C T C3 T3 3 3 C3 T3 C T C T C3 T3 4-29 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number F15 E15 F14 E14 D15 C15 E16 D16 D14 C14 B14 A15 B15 D12 C11 A14 B13 F12 E11 A13 C13 C10 E10 A12 B12 C12 A11 B11 D11 B9 D9 A10 B10 D10 Ball Function GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A GNDIO2 TDO VCCJ TDI TMS TCK GNDIO1 GNDIO1 GNDIO1 PT40B PT40A PT39B GNDIO1 PT39A PT38B PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B PT33A GNDIO1 PT32B PT32A PT31B PT31A PT30B PT29A PT28B PT28A GNDIO1 PT27B Bank Differential 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C3 T 3 LFXP20 Dual Function VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 Ball Function GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A GNDIO2 TDO VCCJ TDI TMS TCK GNDIO1 GNDIO1 GNDIO1 PT44B PT44A PT43B GNDIO1 PT43A PT42B PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B PT37A GNDIO1 PT36B PT36A PT35B PT35A PT34B PT33A PT32B PT32A GNDIO1 PT31B Bank Differential 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C3 T3 C T C T C T C T C T C T C T C T C T C T C Dual Function VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 C T C T C T C T C T C T C T C T C T C T C 4-30 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number A9 C9 C8 E9 B8 A8 A7 B7 C7 E8 D8 A6 C6 E7 D7 A5 B5 A4 B6 E6 D6 D5 A3 B3 B2 A2 B1 F5 C5 C4 B4 C3 A1 A16 F11 F6 Ball Function PT27A PT26B PT26A PT25B GNDIO0 PT25A PT24B PT24A PT23B PT23A PT22B PT21A PT20B GNDIO0 PT20A PT19B PT19A PT18B PT18A PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT13A GNDIO0 PT12B PT12A PT11B PT11A GNDIO0 GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND Bank Differential 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS Ball Function PT31A PT30B PT30A PT29B GNDIO0 PT29A PT28B PT28A PT27B PT27A PT26B PT25A PT24B GNDIO0 PT24A PT23B PT23A PT22B PT22A PT21B PT21A PT20B PT20A PT19B PT19A PT18B PT17A GNDIO0 PT16B PT16A PT15B PT15A GNDIO0 GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND LFXP20 Bank Differential 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS - 4-31 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number G10 G7 G8 G9 H10 H7 H8 H9 J10 J7 J8 J9 K10 K7 K8 K9 L11 L6 T1 T16 D13 D4 E12 E5 M12 M5 N13 N4 E13 E4 M13 M4 F7 F8 F10 F9 G11 H11 J11 K11 L10 L9 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 Bank Differential 0 0 1 1 2 2 3 3 4 4 Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 LFXP20 Bank Differential 0 0 1 1 2 2 3 3 4 4 Dual Function - 4-32 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Number L7 L8 J6 K6 G6 H6 Ball Function VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 Bank Differential 5 5 6 6 7 7 Dual Function Ball Function VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 LFXP20 Bank Differential 5 5 6 6 7 7 Dual Function - 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-33 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA LFXP10 Ball Number F4 G4 D2 D1 E2 E3 F3 F2 H4 H3 G3 G2 F1 E1 J4 K4 G1 H2 J2 H1 J1 K2 K3 J3 K1 L2 L3 L4 L1 M1 M2 N1 M3 M4 P1 N2 R1 P2 N3 N4 T1 R2 Ball Function PROGRAMN CCLK GNDIO7 PL2A PL2B GNDIO7 PL3A PL3B PL4A PL4B PL5A PL6B PL7A PL7B GNDIO7 PL8A PL8B PL9A PL9B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL14A PL15B PL16A GNDIO7 PL16B PL17A PL17B PL18A PL18B VCCP0 GNDP0 PL19A PL19B PL20A GNDIO6 PL20B PL21A PL21B PL22A PL23B PL24A PL24B GNDIO6 Bank Diff. 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS Ball Function PROGRAMN CCLK GNDIO7 PL6A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15A PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL21A PL21B PL22A PL22B VCCP0 GNDP0 PL23A PL23B PL24A GNDIO6 PL24B PL25A PL25B PL26A PL27B PL28A PL28B GNDIO6 LFXP15 Bank Diff. 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS Ball Function PROGRAMN CCLK GNDIO7 PL6A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15A PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL21A PL21B PL22A PL22B VCCP0 GNDP0 PL27A PL27B PL28A GNDIO6 PL28B PL29A PL29B PL30A PL31B PL32A PL32B GNDIO6 LFXP20 Bank Diff. 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T3 C3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS PCLKT6_0 PCLKC6_0 VREF1_6 DQS - 4-34 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number U1 T2 V1 U2 W1 V2 P3 P4 Y1 W2 R3 R4 T3 T4 V4 V3 U4 U3 W5 Y2 Y3 W3 W4 AA2 AA1 W6 W7 Y4 Y5 AB2 AA3 AB3 AA4 W8 W9 AB4 AA5 AB5 Y6 AA6 AB6 Y9 Ball Function PL25A PL25B PL26A PL26B PL28A PL28B GNDIO6 PL29A PL29B PL30A PL30B PL31A PL32B PL33A PL33B GNDIO6 PL34A PL34B PL35A PL35B GNDIO6 SLEEPN1/ 2 TOE INITN GNDIO5 GNDIO5 PB2A PB3A GNDIO5 PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A GNDIO5 PB7B PB8A PB9B PB10A PB10B PB11A Bank Diff. 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T C T C T C T C T C T C T Dual Function LLM0_PLLT_IN_A LLM0_PLLC_IN_A VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A VREF1_5 DQS Ball Function PL29A PL29B PL30A PL30B PL32A PL32B GNDIO6 PL33A PL33B PL34A PL34B PL35A PL36B PL37A PL37B GNDIO6 PL38A PL38B PL39A PL39B GNDIO6 SLEEPN1/ 2 TOE INITN GNDIO5 GNDIO5 PB3B PB4A PB4B PB5A PB6B PB7A PB7B PB8A GNDIO5 PB8B PB9A PB9B PB10A PB10B PB11A PB11B PB12A GNDIO5 PB12B PB13A PB14B PB15A PB15B PB16A LFXP15 Bank Diff. 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T C T C T C T C T C T C T C T C T Dual Function LLM0_PLLT_IN_A LLM0_PLLC_IN_A VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A DQS VREF1_5 DQS Ball Function PL33A PL33B PL34A PL34B PL36A PL36B GNDIO6 PL37A PL37B PL38A PL38B PL39A PL40B PL41A PL41B GNDIO6 PL42A PL42B PL43A PL43B GNDIO6 SLEEPN1/ 2 TOE INITN GNDIO5 GNDIO5 PB7B PB8A PB8B PB9A PB10B PB11A PB11B PB12A GNDIO5 PB12B PB13A PB13B PB14A PB14B PB15A PB15B PB16A GNDIO5 PB16B PB17A PB18B PB19A PB19B PB20A LFXP20 Bank Diff. 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T3 C3 T3 C3 T C T3 C3 T3 C3 T C T3 C3 T C T C T C T C T C T C T C T C T Dual Function LLM0_PLLT_IN_A LLM0_PLLC_IN_A VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A DQS VREF1_5 DQS - 4-35 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number Y10 AA7 AB7 Y7 AA8 AB8 Y8 AB9 AA9 W10 W11 AB10 AA10 AA11 AB11 Y11 Y12 AB12 AA12 AB13 AA13 AA14 AB14 W12 W13 AA15 AB15 AA16 AB16 Y17 AA17 Y13 Y14 AB17 Y18 AA18 AB18 Y19 AB19 AA19 Y20 W14 W15 AB20 Ball Function PB11B PB12A PB12B PB13A GNDIO5 PB13B PB14A PB14B PB15A PB15B PB16A PB17B PB18A PB18B GNDIO5 PB19A PB19B PB20A PB20B PB21A PB21B PB22A PB22B GNDIO4 PB23A PB23B PB24A PB25B PB26A PB26B PB27A PB27B PB28A GNDIO4 PB28B PB29A PB29B PB30A PB30B PB31A PB31B PB32A PB33B GNDIO4 PB34A PB34B PB35A PB35B PB36A Bank Diff. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS Ball Function PB16B PB17A PB17B PB18A GNDIO5 PB18B PB19A PB19B PB20A PB20B PB21A PB22B PB23A PB23B GNDIO5 PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B GNDIO4 PB28A PB28B PB29A PB30B PB31A PB31B PB32A PB32B PB33A GNDIO4 PB33B PB34A PB34B PB35A PB35B PB36A PB36B PB37A PB38B GNDIO4 PB39A PB39B PB40A PB40B PB41A LFXP15 Bank Diff. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS Ball Function PB20B PB21A PB21B PB22A GNDIO5 PB22B PB23A PB23B PB24A PB24B PB25A PB26B PB27A PB27B GNDIO5 PB28A PB28B PB29A PB29B PB30A PB30B PB31A PB31B GNDIO4 PB32A PB32B PB33A PB34B PB35A PB35B PB36A PB36B PB37A GNDIO4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B PB41A PB42B GNDIO4 PB43A PB43B PB44A PB44B PB45A LFXP20 Bank Diff. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 DQS - 4-36 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number AA20 AB21 AA21 AA22 Y21 W16 W17 Y15 Y16 W19 W18 W20 T20 T19 U19 U20 V19 V20 R19 R20 W21 Y22 P19 P20 V21 W22 U21 V22 T21 U22 R21 T22 N19 N20 R22 P22 P21 N21 M20 M19 N22 Ball Function PB36B PB37A PB37B PB38A PB38B GNDIO4 PB39A GNDIO4 GNDIO4 GNDIO3 PR35B PR35A GNDIO3 PR34B PR34A PR33B PR33A PR32B PR31A PR30B PR30A GNDIO3 PR29B PR29A PR28B PR28A PR26B PR26A PR25B PR25A GNDIO3 PR24B PR24A PR23B PR22A PR21B PR21A PR20B PR20A GNDIO3 PR19B PR19A GNDP1 Bank Diff. 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T C C3 T3 C T C3 T3 C3 T 3 LFXP15 Dual Function RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 Ball Function PB41B PB42A PB42B PB43A PB43B GNDIO4 PB44A PB44B PB45A PB46B PB47A PB47B PB48A GNDIO4 GNDIO4 GNDIO3 PR39B PR39A GNDIO3 PR38B PR38A PR37B PR37A PR36B PR35A PR34B PR34A GNDIO3 PR33B PR33A PR32B PR32A PR30B PR30A PR29B PR29A GNDIO3 PR28B PR28A PR27B PR26A PR25B PR25A PR24B PR24A GNDIO3 PR23B PR23A GNDP1 Bank Diff. 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T C T C T C C3 T3 C T C3 T3 C3 T 3 LFXP20 Dual Function DQS RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 Ball Function PB45B PB46A PB46B PB47A PB47B GNDIO4 PB48A PB48B PB49A PB50B PB51A PB51B PB52A GNDIO4 GNDIO4 GNDIO3 PR43B PR43A GNDIO3 PR42B PR42A PR41B PR41A PR40B PR39A PR38B PR38A GNDIO3 PR37B PR37A PR36B PR36A PR34B PR34A PR33B PR33A GNDIO3 PR32B PR32A PR31B PR30A PR29B PR29A PR28B PR28A GNDIO3 PR27B PR27A GNDP1 Bank Diff. 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C T C T C T C C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T3 Dual Function DQS RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 - C T C3 T3 C 3 C T C3 T3 C 3 T3 C T C3 T3 C3 T 3 T3 C T C3 T3 C3 T 3 C T C3 T3 - C T C3 T3 - 4-37 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number M21 M22 L22 K22 K21 L19 K20 L20 L21 J22 J21 H22 H21 K19 J19 J20 H20 H19 G19 G22 G21 F20 G20 F22 F21 E22 E21 D22 D21 F19 E20 D20 D19 D18 E19 D17 D16 C16 C15 C17 C18 C19 Ball Function VCCP1 GNDIO2 PR18B PR18A PR17B PR17A PR16B PR16A PR15B PR14A GNDIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 PR9B PR9A PR8B PR8A PR7B PR7A GNDIO2 PR6B PR5A PR4B PR4A PR3B PR3A PR2B PR2A GNDIO2 TDO VCCJ TDI TMS TCK GNDIO1 PT39A PT38B GNDIO1 Bank Diff. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T 3 LFXP15 Dual Function PCLKC2_0 PCLKT2_0 DQS VREF1_2 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A Ball Function VCCP1 GNDIO2 PR22B PR22A PR21B PR21A PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B PR15A GNDIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A PR6B PR6A GNDIO2 TDO VCCJ TDI TMS TCK GNDIO1 PT48A PT47B PT47A PT46B PT45A PT44B PT44A PT43B GNDIO1 Bank Diff. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T 3 LFXP20 Dual Function PCLKC2_0 PCLKT2_0 DQS VREF1_2 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A DQS Ball Function VCCP1 GNDIO2 PR22B PR22A PR21B PR21A PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B PR15A GNDIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A PR6B PR6A GNDIO2 TDO VCCJ TDI TMS TCK GNDIO1 PT52A PT51B PT51A PT50B PT49A PT48B PT48A PT47B GNDIO1 Bank Diff. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C3 T3 C T C3 T3 C T C T C Dual Function PCLKC2_0 PCLKT2_0 DQS VREF1_2 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A DQS - C3 T3 C T C3 T3 C - C3 T3 C T C3 T3 C T C T C - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4-38 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number C20 C21 C22 B22 A21 D15 D14 B21 A20 B20 A19 B19 A18 C14 C13 B18 A17 B17 A16 B16 A15 B15 A14 D13 D12 B14 A13 B13 A12 B12 C12 C11 B11 A11 A10 B10 B9 D11 D10 A9 C8 B8 A8 C7 Ball Function PT38A PT37B PT37A PT36B PT36A PT35B PT35A PT34B GNDIO1 PT34A PT33B PT32A PT31B PT31A PT30B PT30A PT29B PT29A PT28B PT28A GNDIO1 PT27B PT27A PT26B PT26A PT25B PT24A PT23B PT23A GNDIO1 PT22B PT22A PT21B PT21A PT20B GNDIO0 PT20A PT19B PT19A PT18B PT18A PT17B PT16A PT15B GNDIO0 PT15A PT14B PT14A PT13B Bank Diff. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C Dual Function VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 Ball Function PT43A PT42B PT42A PT41B PT41A PT40B PT40A PT39B GNDIO1 PT39A PT38B PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B PT33A GNDIO1 PT32B PT32A PT31B PT31A PT30B PT29A PT28B PT28A GNDIO1 PT27B PT27A PT26B PT26A PT25B GNDIO0 PT25A PT24B PT24A PT23B PT23A PT22B PT21A PT20B GNDIO0 PT20A PT19B PT19A PT18B LFXP15 Bank Diff. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C Dual Function VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 Ball Function PT47A PT46B PT46A PT45B PT45A PT44B PT44A PT43B GNDIO1 PT43A PT42B PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B PT37A GNDIO1 PT36B PT36A PT35B PT35A PT34B PT33A PT32B PT32A GNDIO1 PT31B PT31A PT30B PT30A PT29B GNDIO0 PT29A PT28B PT28A PT27B PT27A PT26B PT25A PT24B GNDIO0 PT24A PT23B PT23A PT22B LFXP20 Bank Diff. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C Dual Function VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 - 4-39 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number A7 B7 C6 C10 C9 A6 B6 A5 B5 C5 A4 D9 D8 B4 A2 A3 B3 C4 C3 C2 D3 D7 D6 E4 D4 D5 C1 B2 B1 A1 A22 AB1 AB22 H10 H11 H12 H13 H14 J10 J11 J12 J13 J14 J9 K10 Ball Function PT13A PT12B PT12A PT11B PT11A PT10B PT10A PT9B PT8A GNDIO0 PT7B PT7A PT6B PT6A PT5B PT5A PT4B PT4A PT3B PT3A GNDIO0 PT2A GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Diff. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T Dual Function DI CSN VREF2_0 DQS Ball Function PT18A PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT13A GNDIO0 PT12B PT12A PT11B PT11A PT10B PT10A PT9B PT9A PT8B PT8A GNDIO0 PT7B PT7A PT6B PT5A PT4B PT4A PT3B GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFXP15 Bank Diff. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T Dual Function DI CSN VREF2_0 DQS DQS Ball Function PT22A PT21B PT21A PT20B PT20A PT19B PT19A PT18B PT17A GNDIO0 PT16B PT16A PT15B PT15A PT14B PT14A PT13B PT13A PT12B PT12A GNDIO0 PT11B PT11A PT10B PT9A PT8B PT8A PT7B GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFXP20 Bank Diff. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T C T C T C T C T C T C T Dual Function DI CSN VREF2_0 DQS DQS - 4-40 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 R10 R11 R12 R13 R14 H9 J15 J8 K15 K8 L15 L8 M15 M8 N15 N8 P15 P8 R9 G16 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX Bank Diff. Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX LFXP15 Bank Diff. Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX LFXP20 Bank Diff. Dual Function - 4-41 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Number G7 T16 T7 G10 G11 G8 G9 H8 G12 G13 G14 G15 H15 H16 J16 K16 L16 M16 N16 P16 R16 R15 T12 T13 T14 T15 R8 T10 T11 T8 T9 M7 N7 P7 R7 H7 J7 K7 L7 Ball Function VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 Bank Diff. 0 0 0 0 0 1 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function Ball Function VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 LFXP15 Bank Diff. 0 0 0 0 0 1 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function Ball Function VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 LFXP20 Bank Diff. 0 0 0 0 0 1 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function - 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-42 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA LFXP15 Ball Number F5 E3 C1 G5 G6 F4 F3 G4 G3 D1 D2 E1 E2 H5 H6 H4 H3 F1 F2 J5 J6 G1 G2 J4 J3 H1 H2 J1 J2 K3 K2 K4 K5 K1 L2 L4 L3 Ball Function PROGRAMN CCLK PL2B GNDIO7 PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15A PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL21A PL21B PL22A PL22B Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 T 3 LFXP20 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS Ball Function PROGRAMN CCLK PL2B GNDIO7 PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B GNDIO7 PL7A PL7B PL8A PL8B PL9A PL10B PL11A PL11B GNDIO7 PL12A PL12B PL13A PL13B PL15A PL15B GNDIO7 PL16A PL16B PL17A PL17B PL18A PL19B PL20A GNDIO7 PL20B PL21A PL21B PL22A PL22B Bank Differential 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 T 3 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A LUM0_PLLC_IN_A VREF2_7 DQS - C3 T C T3 C T 3 3 C3 T C T3 C3 T 3 C3 T C T3 C3 T3 C T C T3 C T 3 3 3 C3 T C T3 C T3 C T C T3 C3 T 3 3 3 C3 T C T3 C T3 C3 T C T3 C 3 3 C3 T C T3 C T3 C3 T C T3 C3 3 4-43 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number L1 M1 M2 L5 N2 N1 P2 P1 M4 M3 R2 R1 N3 N4 M5 N5 T2 T1 U2 U1 P3 P4 P6 P5 V2 V1 W2 W1 R3 R4 R6 R5 Y2 Y1 T3 T4 W3 V3 Ball Function VCCP0 GNDP0 PL23A PL23B PL24A GNDIO6 PL24B PL25A PL25B PL26A PL27B PL28A PL28B GNDIO6 PL29A PL29B PL30A PL30B PL32A PL32B GNDIO6 PL33A PL33B PL34A PL34B PL35A PL36B PL37A PL37B GNDIO6 PL38A PL38B PL39A PL39B PL40A PL40B Bank Differential 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 T 3 3 LFXP20 Dual Function PCLKT6_0 PCLKC6_0 VREF1_6 DQS LLM0_PLLT_IN_A LLM0_PLLC_IN_A VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A Ball Function PL23A PL23B PL24A VCCP0 GNDP0 PL25B PL26A PL26B PL27A PL27B PL28A GNDIO6 PL28B PL29A PL29B PL30A PL31B PL32A PL32B GNDIO6 PL33A PL33B PL34A PL34B PL36A PL36B GNDIO6 PL37A PL37B PL38A PL38B PL39A PL40B PL41A PL41B GNDIO6 PL42A PL42B PL43A PL43B PL44A PL44B Bank Differential 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 T3 C T3 C3 T3 C C T 3 3 3 Dual Function PCLKT6_0 PCLKC6_0 VREF1_6 DQS LLM0_PLLT_IN_A LLM0_PLLC_IN_A VREF2_6 DQS LLM0_PLLT_FB_A LLM0_PLLC_FB_A - C - T C T 3 T C3 T3 C T C T 3 3 3 C3 T3 C3 T C T 3 3 C C - C C - T3 3 T3 3 T C T3 C T 3 3 T C T3 C3 T 3 C3 T C T3 C C 3 C3 T C T3 C C 3 T3 3 T3 3 4-44 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number T6 T5 U3 U4 V4 W4 W5 Y3 U5 V5 Y4 Y5 V6 U6 W6 Y6 AA2 AA3 V7 U7 Y7 W7 AA4 AA5 AB3 AB4 AA6 AA7 U8 V8 Y8 W8 V9 U9 Y9 W9 Ball Function PL41A PL41B GNDIO6 PL42A PL42B PL43A SLEEPN1/ TOE2 INITN GNDIO5 GNDIO5 PB3A PB3B PB4A PB4B PB5A PB6B PB7A PB7B PB8A GNDIO5 PB8B PB9A PB9B PB10A PB10B PB11A PB11B PB12A GNDIO5 PB12B PB13A PB14B PB15A PB15B Bank Differential 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T 3 LFXP20 Dual Function DQS VREF1_5 DQS Ball Function PL45A PL45B GNDIO6 PL46A PL46B PL47A SLEEPN1/ TOE2 INITN PB3B GNDIO5 PB4A PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A PB8B PB9A PB10B PB11A PB11B PB12A GNDIO5 PB12B PB13A PB13B PB14A PB14B PB15A PB15B PB16A GNDIO5 PB16B PB17A PB18B PB19A PB19B Bank Differential 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 T C T 3 Dual Function DQS VREF1_5 DQS - C3 T C T C T C T C T C T C T C T C T C C3 T C T C T C T C T C T C T C T C T C T C T C T C 4-45 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number AB5 AB6 AA8 AA9 W10 V10 AB7 AB8 AB9 AB10 Y10 AA10 W11 V11 Y11 AA11 AB11 AB12 Y12 AA12 W12 V12 AB13 AB14 AA13 Y13 AB15 AB16 V13 W13 AA14 AA15 AB17 AB18 W14 Y14 U14 V14 Ball Function PB16A PB16B PB17A PB17B PB18A GNDIO5 PB18B PB19A PB19B PB20A PB20B PB21A PB22B PB23A PB23B GNDIO5 PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B GNDIO4 PB28A PB28B PB29A PB30B PB31A PB31B PB32A PB32B PB33A GNDIO4 PB33B PB34A PB34B PB35A PB35B PB36A PB36B Bank Differential 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C Dual Function VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 Ball Function PB20A PB20B PB21A PB21B PB22A GNDIO5 PB22B PB23A PB23B PB24A PB24B PB25A PB26B PB27A PB27B GNDIO5 PB28A PB28B PB29A PB29B PB30A PB30B PB31A PB31B GNDIO4 PB32A PB32B PB33A PB34B PB35A PB35B PB36A PB36B PB37A GNDIO4 PB37B PB38A PB38B PB39A PB39B PB40A PB40B LFXP20 Bank Differential 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C Dual Function VREF2_5 DQS PCLKT4_0 PCLKC4_0 DQS VREF1_4 VREF2_4 - 4-46 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number AB19 AB20 V15 U15 Y15 W15 AA16 AA17 AA18 AA19 Y16 W16 AA20 AA21 Y17 Y18 Y19 Y20 V16 U16 U18 V18 W19 W18 U17 V17 W17 V19 U20 U19 V20 W20 T17 T18 T19 T20 Ball Function PB37A PB38B GNDIO4 PB39A PB39B PB40A PB40B PB41A PB41B PB42A PB42B PB43A PB43B GNDIO4 PB44A PB44B PB45A PB46B PB47A PB47B PB48A PB48B GNDIO4 GNDIO4 GNDIO3 PR43A PR42B PR42A PR41B PR41A PR40B PR40A PR39B PR39A GNDIO3 Bank Differential 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T C T C C3 T 3 LFXP20 Dual Function DQS DQS Ball Function PB41A PB42B GNDIO4 PB43A PB43B PB44A PB44B PB45A PB45B PB46A PB46B PB47A PB47B GNDIO4 PB48A PB48B PB49A PB50B PB51A PB51B PB52A PB52B GNDIO4 PB53A PB53B PB54A PB54B PB55A PB55B GNDIO4 PB56A GNDIO3 PR47A PR46B PR46A PR45B PR45A PR44B PR44A PR43B PR43A GNDIO3 Bank Differential 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 T C T C T C T C T C T C T C T C T C T C T C C3 T3 C T C C 3 Dual Function DQS DQS - C T C 3 T3 C 3 T3 3 T3 T3 4-47 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number R18 R17 Y22 Y21 W22 W21 P17 P18 R19 R20 V22 V21 U22 U21 P19 P20 T22 T21 R22 R21 N19 N20 N18 M18 P22 P21 N22 N21 M19 M20 L18 M21 M22 L22 L19 L20 L21 K22 Ball Function PR38B PR38A PR37B PR37A PR36B PR35A PR34B PR34A GNDIO3 PR33B PR33A PR32B PR32A PR30B PR30A PR29B PR29A GNDIO3 PR28B PR28A PR27B PR26A PR25B PR25A PR24B PR24A GNDIO3 PR23B PR23A GNDP1 VCCP1 PR22B PR22A GNDIO2 PR21B PR21A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 C T C3 T3 C3 T 3 LFXP20 Dual Function RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 Ball Function PR42B PR42A PR41B PR41A PR40B PR39A PR38B PR38A GNDIO3 PR37B PR37A PR36B PR36A PR34B PR34A PR33B PR33A GNDIO3 PR32B PR32A PR31B PR30A PR29B PR29A PR28B PR28A GNDIO3 PR27B PR27A PR26B PR26A PR25B GNDP1 VCCP1 PR24A PR23B PR23A GNDIO2 PR22B PR22A PR21B PR21A Bank Differential 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 C T C3 T 3 Dual Function RLM0_PLLC_FB_A RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A RLM0_PLLT_IN_A DQS VREF2_3 - C3 T 3 C T C C 3 C T C C 3 T3 3 T3 3 T3 C T C3 T3 C3 T 3 T3 C T C3 T3 C3 T 3 C T C C C T 3 3 C T C3 T3 C C C3 T3 C T 3 3 T3 T3 PCLKC2_0 PCLKT2_0 PCLKC2_0 PCLKT2_0 T3 T3 4-48 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number J21 J22 K18 K19 K21 K20 H21 H22 J20 J19 J17 J18 G21 G22 F21 F22 H20 H19 H17 H18 E21 E22 D21 D22 G20 G19 G17 G18 F18 F19 C22 F20 E20 D19 E19 D20 C20 Ball Function PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B PR15A GNDIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A PR4B PR4A GNDIO2 PR3B PR3A PR2B TDO VCCJ TDI TMS TCK GNDIO1 Bank Differential 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 C3 T 3 LFXP20 Dual Function DQS VREF1_2 Ball Function PR20B PR20A PR19B PR18A GNDIO2 PR17B PR17A PR16B PR16A PR15B PR15A GNDIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 PR10B PR9A PR8B PR8A PR7B PR7A PR6B PR6A PR5B PR5A PR4B PR4A GNDIO2 PR3B PR3A PR2B TDO VCCJ TDI TMS TCK PT56A GNDIO1 Bank Differential 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 C3 T 3 Dual Function DQS VREF1_2 - C 3 C 3 RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A - RUM0_PLLC_IN_A RUM0_PLLT_IN_A DQS VREF2_2 RUM0_PLLC_FB_A RUM0_PLLT_FB_A - T3 C T C C T 3 3 3 T3 C T C C T 3 3 3 T3 T3 C T C3 T3 C3 T 3 C T C3 T3 C3 T3 C T C 3 C T C 3 T3 C T 3 3 T3 C3 T 3 C T C3 T3 - C T C3 T3 - 4-49 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number D18 E18 C19 C18 C21 B21 E17 E16 C17 D17 F17 F16 C16 D16 A20 B20 A19 B19 C15 D15 A18 B18 F15 E15 A17 B17 E14 F14 D14 C14 A16 B16 A15 B15 E13 D13 C13 B13 Ball Function GNDIO1 PT48B PT48A PT47B PT47A PT46B PT45A PT44B PT44A PT43B GNDIO1 PT43A PT42B PT42A PT41B PT41A PT40B PT40A PT39B GNDIO1 PT39A PT38B PT37A PT36B PT36A PT35B PT35A PT34B PT34A PT33B PT33A GNDIO1 PT32B PT32A PT31B PT31A Bank Differential 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function DQS VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS Ball Function PT55B PT55A PT54B PT54A PT53B GNDIO1 PT53A PT52B PT52A PT51B PT51A PT50B PT49A PT48B PT48A PT47B GNDIO1 PT47A PT46B PT46A PT45B PT45A PT44B PT44A PT43B GNDIO1 PT43A PT42B PT41A PT40B PT40A PT39B PT39A PT38B PT38A PT37B PT37A GNDIO1 PT36B PT36A PT35B PT35A LFXP20 Bank Differential 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function DQS VREF1_1 DQS D0 D1 VREF2_1 D2 D3 DQS 4-50 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number A14 B14 C12 B12 D12 E12 A13 A12 A11 A10 D11 E11 B11 C11 B9 A9 B8 A8 E10 D10 C10 B10 B7 A7 C9 D9 B6 A6 F9 E9 B5 A5 C8 D8 B4 A4 F8 E8 Ball Function PT30B PT29A PT28B PT28A GNDIO1 PT27B PT27A PT26B PT26A PT25B GNDIO0 PT25A PT24B PT24A PT23B PT23A PT22B PT21A PT20B GNDIO0 PT20A PT19B PT19A PT18B PT18A PT17B PT17A PT16B PT16A PT15B PT15A PT14B PT13A GNDIO0 PT12B PT12A PT11B PT11A PT10B PT10A PT9B PT9A Bank Differential 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS Ball Function PT34B PT33A PT32B PT32A GNDIO1 PT31B PT31A PT30B PT30A PT29B GNDIO0 PT29A PT28B PT28A PT27B PT27A PT26B PT25A PT24B GNDIO0 PT24A PT23B PT23A PT22B PT22A PT21B PT21A PT20B PT20A PT19B PT19A PT18B PT17A GNDIO0 PT16B PT16A PT15B PT15A PT14B PT14A PT13B PT13A LFXP20 Bank Differential 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T C T Dual Function D4 D5 D6 D7 BUSY CS1N PCLKC0_0 PCLKT0_0 DQS DOUT WRITEN VREF1_0 DI CSN VREF2_0 DQS - 4-51 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number B3 A3 D7 C7 B2 C2 C3 D3 F7 E7 C6 D6 C5 C4 F6 E6 E4 E5 D4 D5 A1 A2 A21 A22 AA1 AA22 AB1 AB2 AB21 AB22 B1 B22 H14 H9 J10 J11 J12 J13 J14 Ball Function PT8B PT8A GNDIO0 PT7B PT7A PT6B PT5A PT4B PT4A PT3B PT3A GNDIO0 GNDIO0 CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Differential 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T Dual Function DQS Ball Function PT12B PT12A GNDIO0 PT11B PT11A PT10B PT9A PT8B PT8A PT7B PT7A GNDIO0 PT6B PT6A PT5B PT5A PT4B PT4A GNDIO0 PT3B CFG0 CFG1 DONE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFXP20 Bank Differential 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T Dual Function DQS - 4-52 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number J15 J8 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P15 P8 P9 R14 R9 F10 F13 G10 G13 G14 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC Bank Differential Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC LFXP20 Bank Differential Dual Function - 4-53 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number G9 H15 H8 J16 J7 K16 K17 K6 K7 N16 N17 N6 N7 P16 P7 R15 R8 T10 T13 T14 T9 U10 U13 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 F11 G11 H10 H11 F12 G12 H12 Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 Bank Differential 0 0 0 0 1 1 1 Dual Function Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 LFXP20 Bank Differential 0 0 0 0 1 1 1 Dual Function - 4-54 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Number H13 K15 L15 L16 L17 M15 M16 M17 N15 R12 R13 T12 U12 R10 R11 T11 U11 M6 M7 M8 N8 K8 L6 L7 L8 Ball Function VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 Bank Differential 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function Ball Function VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 LFXP20 Bank Differential 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function - 1. Applies to LFXP "C" only. 2. Applies to LFXP "E" only. 3. Supports dedicated LVDS outputs. 4-55 Lattice Semiconductor Pinout Information LatticeXP Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. * Thermal Management document * Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices * Power Calculator tool included with Lattice's ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-56 LatticeXP Family Data Sheet Ordering Information December 2005 Data Sheet DS1001 Part Number Description LFXP XX X - X XXXXXX X Device Family LatticeXP FPGA Logic Capacity 3K LUTs = 3 6K LUTs = 6 10K LUTs = 10 15K LUTs = 15 20K LUTs = 20 Supply Voltage C = 1.8V/2.5V/3.3V E = 1.2V Note: Parts dual marked per table below. Grade C = Commercial I = Industrial Package T100 = 100-pin TQFP T144 = 144-pin TQFP Q208 = 208-pin PQFP F256 = 256-ball fpBGA F388 = 388-ball fpBGA F484 = 484-ball fpBGA TN100 = 100-pin Lead-free TQFP TN144 = 144-pin Lead-free TQFP QN208 = 208-pin Lead-free PQFP FN256 = 256-ball Lead-free fpBGA FN388 = 388-ball Lead-free fpBGA FN484 = 484-ball Lead-free fpBGA Speed 3 = Slowest 4 5 = Fastest Ordering Information (Contact Factory for Specific Device Availability) Note: LatticeXP devices are dual marked. For example, the commercial speed grade LFXP10E-4F256C is also marked with industrial grade -3I (LFXP10E-3F256I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings. The markings appear as follows: LFXP10E4F256C-3I Datecode (c) 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1001 Ordering Information_03.0 Lattice Semiconductor Conventional Packaging Commercial Part Number LFXP3C-3Q208C LFXP3C-4Q208C LFXP3C-5Q208C LFXP3C-3T144C LFXP3C-4T144C LFXP3C-5T144C LFXP3C-3T100C LFXP3C-4T100C LFXP3C-5T100C I/Os 136 136 136 100 100 100 62 62 62 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Ordering Information LatticeXP Family Data Sheet Pins 208 208 208 144 144 144 100 100 100 Temp. COM COM COM COM COM COM COM COM COM LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6C-3F256C LFXP6C-4F256C LFXP6C-5F256C LFXP6C-3Q208C LFXP6C-4Q208C LFXP6C-5Q208C LFXP6C-3T144C LFXP6C-4T144C LFXP6C-5T144C I/Os 188 188 188 142 142 142 100 100 100 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Pins 256 256 256 208 208 208 144 144 144 Temp. COM COM COM COM COM COM COM COM COM LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10C-3F388C LFXP10C-4F388C LFXP10C-5F388C LFXP10C-3F256C LFXP10C-4F256C LFXP10C-5F256C I/Os 244 244 244 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 388 388 388 256 256 256 Temp. COM COM COM COM COM COM LUTs 9.7K 9.7K 9.7K 9.7K 9.7K 9.7K 5-2 Lattice Semiconductor Commercial (Cont.) Part Number LFXP15C-3F484C LFXP15C-4F484C LFXP15C-5F484C LFXP15C-3F388C LFXP15C-4F388C LFXP15C-5F388C LFXP15C-3F256C LFXP15C-4F256C LFXP15C-5F256C I/Os 300 300 300 268 268 268 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20C-3F484C LFXP20C-4F484C LFXP20C-5F484C LFXP20C-3F388C LFXP20C-4F388C LFXP20C-5F388C LFXP20C-3F256C LFXP20C-4F256C LFXP20C-5F256C I/Os 340 340 340 268 268 268 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Part Number LFXP3E-3Q208C LFXP3E-4Q208C LFXP3E-5Q208C LFXP3E-3T144C LFXP3E-4T144C LFXP3E-5T144C LFXP3E-3T100C LFXP3E-4T100C LFXP3E-5T100C I/Os 136 136 136 100 100 100 62 62 62 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Pins 208 208 208 144 144 144 100 100 100 Temp. COM COM COM COM COM COM COM COM COM LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 5-3 Lattice Semiconductor Commercial (Cont.) Part Number LFXP6E-3F256C LFXP6E-4F256C LFXP6E-5F256C LFXP6E-3Q208C LFXP6E-4Q208C LFXP6E-5Q208C LFXP6E-3T144C LFXP6E-4T144C LFXP6E-5T144C I/Os 188 188 188 142 142 142 100 100 100 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Ordering Information LatticeXP Family Data Sheet Pins 256 256 256 208 208 208 144 144 144 Temp. COM COM COM COM COM COM COM COM COM LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10E-3F388C LFXP10E-4F388C LFXP10E-5F388C LFXP10E-3F256C LFXP10E-4F256C LFXP10E-5F256C I/Os 244 244 244 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 388 388 388 256 256 256 Temp. COM COM COM COM COM COM LUTs 9.7K 9.7K 9.7K 9.7K 9.7K 9.7K Part Number LFXP15E-3F484C LFXP15E-4F484C LFXP15E-5F484C LFXP15E-3F388C LFXP15E-4F388C LFXP15E-5F388C LFXP15E-3F256C LFXP15E-4F256C LFXP15E-5F256C I/Os 300 300 300 268 268 268 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 5-4 Lattice Semiconductor Commercial (Cont.) Part Number LFXP20E-3F484C LFXP20E-4F484C LFXP20E-5F484C LFXP20E-3F388C LFXP20E-4F388C LFXP20E-5F388C LFXP20E-3F256C LFXP20E-4F256C LFXP20E-5F256C I/Os 340 340 340 268 268 268 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Industrial Part Number LFXP3C-3Q208I LFXP3C-4Q208I LFXP3C-3T144I LFXP3C-4T144I LFXP3C-3T100I LFXP3C-4T100I I/Os 136 136 100 100 62 62 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package PQFP PQFP TQFP TQFP TQFP TQFP Pins 208 208 144 144 100 100 Temp. IND IND IND IND IND IND LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6C-3F256I LFXP6C-4F256I LFXP6C-3Q208I LFXP6C-4Q208I LFXP6C-3T144I LFXP6C-4T144I I/Os 188 188 142 142 100 100 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA PQFP PQFP TQFP TQFP Pins 256 256 208 208 144 144 Temp. IND IND IND IND IND IND LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10C-3F388I LFXP10C-4F388I LFXP10C-3F256I LFXP10C-4F256I I/Os 244 244 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Pins 388 388 256 256 Temp. IND IND IND IND LUTs 9.7K 9.7K 9.7K 9.7K 5-5 Lattice Semiconductor Industrial (Cont.) Part Number LFXP15C-3F484I LFXP15C-4F484I LFXP15C-3F388I LFXP15C-4F388I LFXP15C-3F256I LFXP15C-4F256I I/Os 300 300 268 268 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20C-3F484I LFXP20C-4F484I LFXP20C-3F388I LFXP20C-4F388I LFXP20C-3F256I LFXP20C-4F256I I/Os 340 340 268 268 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Part Number LFXP3E-3Q208I LFXP3E-4Q208I LFXP3E-3T144I LFXP3E-4T144I LFXP3E-3T100I LFXP3E-4T100I I/Os 136 136 100 100 62 62 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package PQFP PQFP TQFP TQFP TQFP TQFP Pins 208 208 144 144 100 100 Temp. IND IND IND IND IND IND LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6E-3F256I LFXP6E-4F256I LFXP6E-3Q208I LFXP6E-4Q208I LFXP6E-3T144I LFXP6E-4T144I I/Os 188 188 142 142 100 100 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA PQFP PQFP TQFP TQFP Pins 256 256 208 208 144 144 Temp. IND IND IND IND IND IND LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10E-3F388I LFXP10E-4F388I LFXP10E-3F256I LFXP10E-4F256I I/Os 244 244 188 188 Voltage 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Pins 388 388 256 256 Temp. IND IND IND IND LUTs 9.7K 9.7K 9.7K 9.7K 5-6 Lattice Semiconductor Industrial (Cont.) Part Number LFXP15E-3F484I LFXP15E-4F484I LFXP15E-3F388I LFXP15E-4F388I LFXP15E-3F256I LFXP15E-4F256I I/Os 300 300 268 268 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20E-3F484I LFXP20E-4F484I LFXP20E-3F388I LFXP20E-4F388I LFXP20E-3F256I LFXP20E-4F256I I/Os 340 340 268 268 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 5-7 Lattice Semiconductor Lead-free Packaging Commercial Part Number LFXP3C-3QN208C LFXP3C-4QN208C LFXP3C-5QN208C LFXP3C-3TN144C LFXP3C-4TN144C LFXP3C-5TN144C LFXP3C-3TN100C LFXP3C-4TN100C LFXP3C-5TN100C I/Os 136 136 136 100 100 100 62 62 62 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Ordering Information LatticeXP Family Data Sheet Pins 208 208 208 144 144 144 100 100 100 Temp. COM COM COM COM COM COM COM COM COM LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6C-3FN256C LFXP6C-4FN256C LFXP6C-5FN256C LFXP6C-3QN208C LFXP6C-4QN208C LFXP6C-5QN208C LFXP6C-3TN144C LFXP6C-4TN144C LFXP6C-5TN144C I/Os 188 188 188 142 142 142 100 100 100 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Pins 256 256 256 208 208 208 144 144 144 Temp. COM COM COM COM COM COM COM COM COM LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10C-3FN388C LFXP10C-4FN388C LFXP10C-5FN388C LFXP10C-3FN256C LFXP10C-4FN256C LFXP10C-5FN256C I/Os 244 244 244 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 388 388 388 256 256 256 Temp. COM COM COM COM COM COM LUTs 9.7K 9.7K 9.7K 9.7K 9.7K 9.7K Part Number LFXP15C-3FN484C LFXP15C-4FN484C LFXP15C-5FN484C LFXP15C-3FN388C LFXP15C-4FN388C LFXP15C-5FN388C LFXP15C-3FN256C LFXP15C-4FN256C LFXP15C-5FN256C I/Os 300 300 300 268 268 268 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 5-8 Lattice Semiconductor Commercial (Cont.) Part Number LFXP20C-3FN484C LFXP20C-4FN484C LFXP20C-5FN484C LFXP20C-3FN388C LFXP20C-4FN388C LFXP20C-5FN388C LFXP20C-3FN256C LFXP20C-4FN256C LFXP20C-5FN256C I/Os 340 340 340 268 268 268 188 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Part Number LFXP3E-3QN208C LFXP3E-4QN208C LFXP3E-5QN208C LFXP3E-3TN144C LFXP3E-4TN144C LFXP3E-5TN144C LFXP3E-3TN100C LFXP3E-4TN100C LFXP3E-5TN100C I/Os 136 136 136 100 100 100 62 62 62 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package PQFP PQFP PQFP TQFP TQFP TQFP TQFP TQFP TQFP Pins 208 208 208 144 144 144 100 100 100 Temp. COM COM COM COM COM COM COM COM COM LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6E-3FN256C LFXP6E-4FN256C LFXP6E-5FN256C LFXP6E-3QN208C LFXP6E-4QN208C LFXP6E-5QN208C LFXP6E-3TN144C LFXP6E-4TN144C LFXP6E-5TN144C I/Os 188 188 188 142 142 142 100 100 100 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA PQFP PQFP PQFP TQFP TQFP TQFP Pins 256 256 256 208 208 208 144 144 144 Temp. COM COM COM COM COM COM COM COM COM LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K Part Number LFXP10E-3FN388C LFXP10E-4FN388C LFXP10E-5FN388C LFXP10E-3FN256C LFXP10E-4FN256C LFXP10E-5FN256C I/Os 244 244 244 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 388 388 388 256 256 256 Temp. COM COM COM COM COM COM LUTs 9.7K 9.7K 9.7K 9.7K 9.7K 9.7K 5-9 Lattice Semiconductor Commercial (Cont.) Part Number LFXP15E-3FN484C LFXP15E-4FN484C LFXP15E-5FN484C LFXP15E-3FN388C LFXP15E-4FN388C LFXP15E-5FN388C LFXP15E-3FN256C LFXP15E-4FN256C LFXP15E-5FN256C I/Os 300 300 300 268 268 268 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20E-3FN484C LFXP20E-4FN484C LFXP20E-5FN484C LFXP20E-3FN388C LFXP20E-4FN388C LFXP20E-5FN388C LFXP20E-3FN256C LFXP20E-4FN256C LFXP20E-5FN256C I/Os 340 340 340 268 268 268 188 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -5 -3 -4 -5 -3 -4 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 388 388 388 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Industrial Part Number LFXP3C-3QN208I LFXP3C-4QN208I LFXP3C-3TN144I LFXP3C-4TN144I LFXP3C-3TN100I LFXP3C-4TN100I I/Os 136 136 100 100 62 62 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package PQFP PQFP TQFP TQFP TQFP TQFP Pins 208 208 144 144 100 100 Temp. IND IND IND IND IND IND LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6C-3FN256I LFXP6C-4FN256I LFXP6C-3QN208I LFXP6C-4QN208I LFXP6C-3TN144I LFXP6C-4TN144I I/Os 188 188 142 142 100 100 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA PQFP PQFP TQFP TQFP Pins 256 256 208 208 144 144 Temp. IND IND IND IND IND IND LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5-10 Lattice Semiconductor Industrial (Cont.) Part Number LFXP10C-3FN388I LFXP10C-4FN388I LFXP10C-3FN256I LFXP10C-4FN256I I/Os 244 244 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 388 388 256 256 Temp. IND IND IND IND LUTs 9.7K 9.7K 9.7K 9.7K Part Number LFXP15C-3FN484I LFXP15C-4FN484I LFXP15C-3FN388I LFXP15C-4FN388I LFXP15C-3FN256I LFXP15C-4FN256I I/Os 300 300 268 268 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20C-3FN484I LFXP20C-4FN484I LFXP20C-3FN388I LFXP20C-4FN388I LFXP20C-3FN256I LFXP20C-4FN256I I/Os 340 340 268 268 188 188 Voltage 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V 1.8/2.5/3.3V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K Part Number LFXP3E-3QN208I LFXP3E-4QN208I LFXP3E-3TN144I LFXP3E-4TN144I LFXP3E-3TN100I LFXP3E-4TN100I I/Os 136 136 100 100 62 62 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package PQFP PQFP TQFP TQFP TQFP TQFP Pins 208 208 144 144 100 100 Temp. IND IND IND IND IND IND LUTs 3.1K 3.1K 3.1K 3.1K 3.1K 3.1K Part Number LFXP6E-3FN256I LFXP6E-4FN256I LFXP6E-3QN208I LFXP6E-4QN208I LFXP6E-3TN144I LFXP6E-4TN144I I/Os 188 188 142 142 100 100 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA PQFP PQFP TQFP TQFP Pins 256 256 208 208 144 144 Temp. IND IND IND IND IND IND LUTs 5.8K 5.8K 5.8K 5.8K 5.8K 5.8K 5-11 Lattice Semiconductor Industrial (Cont.) Part Number LFXP10E-3FN388I LFXP10E-4FN388I LFXP10E-3FN256I LFXP10E-4FN256I I/Os 244 244 188 188 Voltage 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeXP Family Data Sheet Pins 388 388 256 256 Temp. IND IND IND IND LUTs 9.7K 9.7K 9.7K 9.7K Part Number LFXP15E-3FN484I LFXP15E-4FN484I LFXP15E-3FN388I LFXP15E-4FN388I LFXP15E-3FN256I LFXP15E-4FN256I I/Os 300 300 268 268 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 15.5K 15.5K 15.5K 15.5K 15.5K 15.5K Part Number LFXP20E-3FN484I LFXP20E-4FN484I LFXP20E-3FN388I LFXP20E-4FN388I LFXP20E-3FN256I LFXP20E-4FN256I I/Os 340 340 268 268 188 188 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -3 -4 -3 -4 -3 -4 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 388 388 256 256 Temp. IND IND IND IND IND IND LUTs 19.7K 19.7K 19.7K 19.7K 19.7K 19.7K 5-12 LatticeXP Family Data Sheet Supplemental Information November 2007 Data Sheet DS1001 For Further Information A variety of technical notes for the LatticeXP family are available on the Lattice website at www.latticesemi.com. * * * * * * * LatticeECP/EC and LatticeXP sysIO Usage Guide (TN1056) Lattice ispTRACY Usage Guide (TN1054) LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide (TN1049) Memory Usage Guide for LatticeECP/EC and LatticeXP Devices (TN1051) LatticeECP/EC and XP DDR Usage Guide (TN1050) Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052) LatticeXP sysCONFIG Usage Guide (TN1082) For further information on interface standards refer to the following web sites: * JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org * PCI: www.pcisig.com (c) 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1001 Further Information_01.3 LatticeXP Family Data Sheet Revision History November 2007 Data Sheet DS1001 Revision History Date February 2005 April 2005 May 2005 June 2005 July 2005 Version 01.0 01.1 01.2 01.3 02.0 Section -- Architecture Introduction Architecture Pinout Information Introduction Architecture Initial release. EBR memory support section updated with clarification. Added TransFR Reconfiguration to Features section. Added TransFR section. Added pinout information for LFXP3, LFXP6, LFXP15 and LFXP20. Updated XP6, XP15 and XP20 EBR SRAM Bits and Block numbers. Updated Per Quadrant Primary Clock Selection figure. Added Typical I/O Behavior During Power-up section. Updated Device Configuration section under Configuration and Testing. DC and Switching Characteristics Clarified Hot Socketing Specification Updated Supply Current (Standby) Table Updated Initialization Supply Current Table Added Programming and Erase Flash Supply Current table Added LVDS Emulation section. Updated LVDS25E Output Termination Example figure and LVDS25E DC Conditions table. Updated Differential LVPECL diagram and LVPECL DC Conditions table. Deleted 5V Tolerant Input Buffer section. Updated RSDS figure and RSDS DC Conditions table. Updated sysCONFIG Port Timing Specifications Updated JTAG Port Timing Specifications. Added Flash Download Time table. Pinout Information Ordering Information July 2005 August 2005 02.1 02.2 DC and Switching Characteristics Introduction Architecture DC and Switching Characteristics Pinout Information Updated Signal Descriptions table. Updated Logic Signal Connections Dual Function column. Added lead-free ordering part numbers. Clarification of Flash Programming Junction Temperature Added Sleep Mode feature. Added Sleep Mode section. Added Sleep Mode Supply Current Table Added Sleep Mode Timing section Added SLEEPN and TOE signal names, descriptions and footnotes. Added SLEEPN and TOE to pinout information and footnotes. Added footnote 3 to Logic Signal Connections tables for clarification on emulated LVDS output. September 2005 03.0 Architecture DC and Switching Characteristics Added clarification of PCI clamp. Added clarification to SLEEPN Pin Characteristics section. DC Characteristics, added footnote 4 for clarification. Updated Supply Current (Sleep Mode), Supply Current (Standby), Initialization Supply Current, and Programming and Erase Flash Supply Current typical numbers. Change Summary (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Lattice Semiconductor Date September 2005 (cont.) Version 03.0 (cont.) Section Revision History LatticeXP Family Data Sheet Change Summary DC and Switching Updated Typical Building Block Function Performance timing numbers. Characteristics (cont.) Updated External Switching Characteristics timing numbers. Updated Internal Timing Parameters. Updated LatticeXP Family timing adders. Updated LatticeXP "C" Sleep Mode timing numbers. Updated JTAG Port Timing numbers. Pinout Information Supplemental Information Added clarification to SLEEPN and TOE description. Clarification of dedicated LVDS outputs. Updated list of technical notes. Power Supply and NC Connections table corrected VCCP1 pin number for 208 PQFP. Moved data sheet from Advance to Final. Added clarification to Typical I/O Behavior During Power-up section. Added clarification to Recommended Operating Conditions. Updated timing numbers. Pinout Information Updated Signal Descriptions table. Added clarification to Differential I/O Per Bank. Updated Differential dedicated LVDS output support. Ordering Information Added 208 PQFP lead-free package and ordering part numbers. Corrected description of Signal Names VREF1(x) and VREF2(x). Corrected condition for IIL and IIH. Added clarification to Recommended Operating Conditions for VCCAUX. Removed Bank designator "5" from SLEEPN/TOE ball function. Added footnote 2 regarding threshold level for PROGRAMN to sysCONFIG Port Timing Specifications table. Corrected LVDS25E Output Termination Example. Added clarification to Typical I/O Behavior During Power-Up section. Added clarification to Left and Right sysIO Buffer Pair section. DC and Switching Characteristics Changes to LVDS25E Output Termination Example diagram. EBR Asynchronous Reset section added. Updated EBR Asynchronous Reset section. Updated LatticeXP Family Selection Guide table. Updated Typical I/O Behavior During Power-up text section. Updated sysIO Single-Ended DC Electrical Characteristics table. Split out LVCMOS 1.2 by supply voltage. Added JTAG Port Timing Waveforms diagram. Added Thermal Management text section. Updated title list. September 2005 December 2005 03.1 04.0 Pinout Information Introduction Architecture DC and Switching Characteristics February 2006 March 2006 March 2006 April 2006 May 2006 June 2006 August 2006 04.1 04.2 04.3 04.4 04.5 04.6 04.7 Pinout Information DC and Switching Characteristics DC and Switching Characteristics Pinout Information DC and Switching Characteristics DC and Switching Characteristics Architecture December 2006 February 2007 July 2007 04.8 04.9 05.0 Architecture Architecture Introduction Architecture DC and Switching Characteristics November 2007 05.1 DC and Switching Characteristics Pinout Information Supplemental Information 7-2 |
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